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? 2007 microchip technology inc. preliminary ds41288c pic16f610/16hv610 PIC16F616/16hv616 data sheet 14-pin, flash-based 8-bit cmos microcontrollers
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? 2007 microchip technology inc. preliminary ds41288c-page 1 pic16f610/616/16hv610/616 high-performance risc cpu: ? only 35 instructions to learn: - all single-cycle instructions except branches ? operating speed: - dc ? 20 mhz oscillator/clock input - dc ? 200 ns instruction cycle ? interrupt capability ? 8-level deep hardware stack ? direct, indirect and relative addressing modes special microcontroller features: ? precision internal oscillator: - factory calibrated to 1%, typical - user selectable frequency: 4 mhz or 8 mhz ? power-saving sleep mode ? voltage range: - pic16f610/616: 2.0v to 5.5v - pic16hv610/616: 2.0v to user defined maximum (see note) ? industrial and extended temperature range ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? brown-out reset (bor) ? watchdog timer (wdt) with independent oscillator for reliable operation ? multiplexed master clear with pull-up/input pin ? programmable code protection ? high endurance flash: - 100,000 write flash endurance - flash retention: > 40 years low-power features: ? standby current: - 50 na @ 2.0v, typical ? operating current: -20 a @ 32 khz, 2.0v, typical -220 a @ 4 mhz, 2.0v, typical ? watchdog timer current: -1 a @ 2.0v, typical note: voltage across internal shunt regulator cannot exceed 5v. peripheral features: ? shunt voltage regulator (pic16hv610/616 only): - 5 volt regulation - 4 ma to 50 ma shunt range ? 11 i/o pins and 1 input only - high current source/sink for direct led drive - interrupt-on-change pins - individually programmable weak pull-ups ? analog comparator module with: - two analog comparators - programmable on-chip voltage reference (cv ref ) module (% of v dd ) - fixed voltage reference - comparator inputs and outputs externally accessible -sr latch - built-in hysteresis (user selectable) ? timer0: 8-bit timer/counter with 8-bit programmable prescaler ? enhanced timer1: - 16-bit timer/counter with prescaler - external timer1 gate (count enable) - option to use osc1 and osc2 in lp mode as timer1 oscillator if intosc mode selected - timer1 oscillator ? in-circuit serial programming tm (icsp tm ) via two pins PIC16F616/16hv616 only: ? a/d converter: - 10-bit resolution - 8 external input channels - 2 internal reference channels ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? enhanced capture, compare, pwm module: - 16-bit capture, max. resolution 12.5 ns - 16-bit compare, max. resolution 200 ns - 10-bit pwm with 1, 2 or 4 output channels, programmable ?dead time?, max. frequency 20 khz 14-pin flash-based, 8-bi t cmos microcontrollers
pic16f610/616/16hv610/616 ds41288c-page 2 preliminary ? 2007 microchip technology inc. pic16f610/16hv610 14-pin diagram (pdip, soic, tssop) table 1: pic16f610/16hv610 14- pin summary device program memory data memory i/o 10-bit a/d (ch) comparators timers 8/16-bit voltage range flash (words) sram (bytes) pic16f610 1024 64 11 ? 2 1/1 2.0-5.5v pic16hv610 1024 64 11 ? 2 1/1 2.0-user defined PIC16F616 2048 128 11 8 2 2/1 2.0-5.5v pic16hv616 2048 128 11 8 2 2/1 2.0-user defined i/o pin comparators timer interrupts pull-ups basic ra0 13 c1in+ ? ioc y icspdat ra1 12 c12in0- ? ioc y icspclk ra2 11 c1out t0cki int/ioc y ? ra3 (1) 4? ?iocy (2) mclr /v pp ra4 3 ? t1g ioc y osc2/clkout ra5 2 ? t1cki ioc y osc1/clkin rc0 10 c2in+ ? ? ? ? rc1 9 c12in1- ? ? ? ? rc2 8 c12in2- ? ? ? ? rc3 7 c12in3- ? ? ? ? rc4 6 c2out ? ? ? ? rc5 5 ? ? ? ? ? ? 1 ? ? ? ? v dd ?14 ? ? ? ? v ss note 1: input only. 2: only when pin is configured for external mclr . v dd ra5/t1cki/osc1/clkin ra4/t1g /osc2/clkout ra3/mclr /v pp rc5 rc4/c2out rc3/c12in3- v ss ra0/c1in+/icspdat ra1/c12in0-/icspclk ra2/t0cki/int/c1out rc0/c2in+ rc1/c12in1- rc2/c12in2- pic16f610/16hv610 1 2 3 4 5 6 7 14 13 12 9 11 10 8
? 2007 microchip technology inc. preliminary ds41288c-page 3 pic16f610/616/16hv610/616 PIC16F616/16hv616 14-pin diagram (pdip, soic, tssop) table 2: PIC16F616/16hv616 14- pin summary i/o pin analog comparators timer ccp interrupts pull-ups basic ra0 13 an0 c1in+ ? ? ioc y icspdat ra1 12 an1/v ref c12in0- ? ? ioc y icspclk ra2 11 an2 c1out t0cki ? int/ioc y ? ra3 (1) 4? ? ? ? iocy (2) mclr /v pp ra4 3 an3 ? t1g ? ioc y osc2/clkout ra5 2 ? ? t1cki ? ioc y osc1/clkin rc0 10 an4 c2in+ ? ? ? ? ? rc1 9 an5 c12in1- ? ? ? ? ? rc2 8 an6 c12in2- ? p1d ? ? ? rc3 7 an7 c12in3- ? p1c ? ? ? rc4 6 ? c2out ? p1b ? ? ? rc5 5 ? ? ? ccp1/p1a ? ? ? ? 1 ? ? ? ? ? ? v dd ?14 ? ? ? ? ? ? v ss note 1: input only. 2: only when pin is configured for external mclr . v dd ra5/t1cki/osc1/clkin ra4/an3/t1g /osc2/clkout ra3/mclr /v pp rc5/ccp1/p1a rc4/c2out/p1b rc3/an7/c12in3-/p1c v ss ra0/an0/c1in+/icspdat ra1/an1/c12in0-/v ref /icspclk ra2/an2/t0cki/int/c1out rc0/an4/c2in+ rc1/an5/c12in1- rc2/an6/c12in2-/p1d PIC16F616/16hv616 1 2 3 4 5 6 7 14 13 12 9 11 10 8
pic16f610/616/16hv610/616 ds41288c-page 4 preliminary ? 2007 microchip technology inc. pic16f610/16hv610 16-pin diagram (qfn) table 3: pic16f610/16hv610 16- pin summary i/o pin comparators timers interrupts pull-ups basic ra0 12 c1in+ ? ioc y icspdat ra1 11 c12in0- ? ioc y icspclk ra2 10 c1out t0cki int/ioc y ? ra3 (1) 3? ?iocy (2) mclr /v pp ra4 2 ? t1g ioc y osc2/clkout ra5 1 ? t1cki ioc y osc1/clkin rc0 9 c2in+ ? ? ? ? rc1 8 c12in1- ? ? ? ? rc2 7 c12in2- ? ? ? ? rc3 6 c12in3- ? ? ? ? rc4 5 c2out ? ? ? ? rc5 4 ? ? ? ? ? ? 16 ? ? ? ? v dd ?13 ? ? ? ? v ss note 1: input only. 2: only when pin is configured for external mclr . 1 2 3 4 9 10 11 12 5 6 7 8 16 15 14 13 pic16f610/ pic16hv610 ra5/t1cki/osc1/clkin ra4/t1g /osc2/clkout ra3/mclr /v pp rc5 v dd nc nc v ss ra0/c1in+/icspdat ra1/c12in0-/icspclk ra2/t0cki/int/c1out rc0/c2in1+ rc4/c2out rc3/c12in3- rc2/c12in2- rc1/c12in1-
? 2007 microchip technology inc. preliminary ds41288c-page 5 pic16f610/616/16hv610/616 PIC16F616/16hv616 16-pin diagram (qfn) table 4: PIC16F616/16hv616 16- pin summary i/o pin analog comparators timers ccp interrupts pull-ups basic ra0 12 an0 c1in+ ? ? ioc y icspdat ra1 11 an1/v ref c12in0- ? ? ioc y icspclk ra2 10 an2 c1out t0cki ? int/ioc y ? ra3 (1) 3? ? ? ? iocy (2) mclr /v pp ra4 2 an3 ? t1g ? ioc y osc2/clkout ra5 1 ? ? t1cki ? ioc y osc1/clkin rc0 9 an4 c2in+ ? ? ? ? ? rc1 8 an5 c12in1- ? ? ? ? ? rc2 7 an6 c12in2- ? p1d ? ? ? rc3 6 an7 c12in3- ? p1c ? ? ? rc4 5 ? c2out ? p1b ? ? ? rc5 4 ? ? ? ccp1/p1a ? ? ? ? 16 ? ? ? ? ? ? v dd ?13 ? ? ? ? ? ? v ss note 1: input only. 2: only when pin is configured for external mclr . 1 2 3 4 9 10 11 12 5 6 7 8 16 15 14 13 PIC16F616/ pic16hv616 ra5/t1cki/osc1/clkin ra4/an3/t1g /osc2/clkout ra3/mclr /v pp rc5/ccp/p1a v dd nc nc v ss ra0/an0/c1in+/icspdat ra1/an1/c12in0-/v ref /icspclk ra2/an2/t0cki/int/c1out rc0/an4/c2in1+ rc4/c2out/p1b rc3/an7/c12in3-/p1c rc2/an6/c12in2-/p1d rc1/an5/c12in1-
pic16f610/616/16hv610/616 ds41288c-page 6 preliminary ? 2007 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 memory organization ......................................................................................................... ........................................................ 11 3.0 oscillator module........................................................................................................... ............................................................. 25 4.0 i/o ports ................................................................................................................... .................................................................. 31 5.0 timer0 module ............................................................................................................... ............................................................ 43 6.0 timer1 module with gate control............................................................................................. .................................................. 47 7.0 timer2 module ............................................................................................................... ............................................................ 53 8.0 comparator module........................................................................................................... ......................................................... 55 9.0 analog-to-digital converter (adc) module .................................................................................... ............................................ 71 10.0 enhanced capture/compare/pwm (with auto-shutdown and dead band) module ..................................................... ............ 83 11.0 voltage regulator.......................................................................................................... ........................................................... 105 12.0 special features of the cpu ................................................................................................ .................................................... 106 13.0 instruction set summary .................................................................................................... ...................................................... 125 14.0 development support........................................................................................................ ....................................................... 135 15.0 electrical specifications.................................................................................................. .......................................................... 139 16.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 161 17.0 packaging information...................................................................................................... ........................................................ 163 appendix a: data sheet revision history........................................................................................ .................................................. 169 appendix b: migrating from other pic ? devices....................................................................................................................... ......... 169 index .......................................................................................................................... ........................................................................ 171 the microchip web site ......................................................................................................... ............................................................ 175 customer change notification service ........................................................................................... ................................................... 175 customer support ............................................................................................................... ............................................................... 175 reader response ................................................................................................................ .............................................................. 176 product identification system.................................................................................................. ........................................................... 177 to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues bec ome known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? 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? 2007 microchip technology inc. preliminary ds41288c-page 7 pic16f610/616/16hv610/616 1.0 device overview the pic16f610/616/16hv610/616 is covered by this data sheet. it is available in 14-pin pdip, soic, tssop and 16-pin qfn packages. block diagrams and pinout descriptions of the devices are as follows: ? pic16f610/16hv610 (figure 1-1, table 1-1) ? PIC16F616/16hv616 (figure 1-2, table 1-2) figure 1-1: pic16f610/16hv610 block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter ram file registers direct addr 7 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode and control timing generation osc1/clkin osc2/clkout porta 8 8 8 3 8-level stack 64 bytes 1k x 14 (13-bit) power-up timer oscillator start-up timer power-on reset watchdog timer mclr v ss brown-out reset timer0 timer1 ra0 ra1 ra2 ra3 ra4 ra5 2 analog comparators t0cki int t1cki configuration internal oscillator t1g portc v dd block shunt regulator ( pic16hv610 only) rc0 rc1 rc2 rc3 rc4 rc5 c1in+ c12in0- c12in1- c12in2- c12in3- c1out c2in+ c2out comparator voltage reference fixed voltage reference
pic16f610/616/16hv610/616 ds41288c-page 8 preliminary ? 2007 microchip technology inc. figure 1-2: PIC16F616/16hv616 block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter ram file registers direct addr 7 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode and control timing generation osc1/clkin osc2/clkout porta 8 8 8 3 8-level stack 128 bytes 2k x 14 (13-bit) power-up timer oscillator start-up timer power-on reset watchdog timer mclr v ss brown-out reset timer0 timer1 ra0 ra1 ra2 ra3 ra4 ra5 2 analog comparators t0cki int t1cki configuration internal oscillator v ref t1g portc v dd timer2 block shunt regulator ( pic16hv616 only) analog-to-digital converter rc0 rc1 rc2 rc3 rc4 rc5 an0 an1 an2 an3 an4 an5 an6 an7 c1in+ c12in0- c12in1- c12in2- c12in3- c1out c2in+ c2out eccp ccp1/p1a p1b p1c p1d comparator voltage reference fixed voltage reference
? 2007 microchip technology inc. preliminary ds41288c-page 9 pic16f610/616/16hv610/616 table 1-1: pic16f610/16hv610 pinout description name function input ty pe output type description ra0/c1in+/icspdat ra0 ttl cmos porta i/o with prog. pull-up and interrupt-on-change c1in+ an ? comparator c1 non-inverting input icspdat st cmos serial programming data i/o ra1/c12in0-/icspclk ra1 ttl cmos porta i/o with prog. pull-up and interrupt-on-change c12in0- an ? comparators c1 and c2 inverting input icspclk st ? serial programming clock ra2/t0cki/int/c1out ra2 st cmos porta i/o with prog. pull-up and interrupt-on-change t0cki st ? timer0 clock input int st ? external interrupt c1out ? cmos comparator c1 output ra3/mclr /v pp ra3 ttl ? porta input with interrupt-on-change mclr st ? master clear w/internal pull-up v pp hv ? programming voltage ra4/t1g /osc2/clkout ra4 ttl cmos porta i/o with prog. pull-up and interrupt-on-change t1g st ? timer1 gate (count enable) osc2 ? xtal crystal/resonator clkout ? cmos f osc /4 output ra5/t1cki/osc1/clkin ra5 ttl cmos porta i/o with prog. pull-up and interrupt-on-change t1cki st ? timer1 clock input osc1 xtal ? crystal/resonator clkin st ? external clock input/rc oscillator connection rc0/c2in+ rc0 ttl cmos portc i/o c2in+ an ? comparator c2 non-inverting input rc1/c12in1- rc1 ttl cmos portc i/o c12in1- an ? comparators c1 and c2 inverting input rc2/c12in2- rc2 ttl cmos portc i/o c12in2- an ? comparators c1 and c2 inverting input rc3/c12in3- rc3 ttl cmos portc i/o c12in3- an ? comparators c1 and c2 inverting input rc4/c2out rc4 ttl cmos portc i/o c2out ? cmos comparator c2 output rc5 rc5 ttl cmos portc i/o v dd v dd power ? positive supply v ss v ss power ? ground reference legend: an = analog input or output cmos = cmos compatible input or output hv = high voltage st = schmitt trigger input with cmos levels ttl = ttl compatible input xtal = crystal
pic16f610/616/16hv610/616 ds41288c-page 10 preliminary ? 2007 microchip technology inc. table 1-2: PIC16F616/16hv616 pinout description name function input ty pe output type description ra0/an0/c1in+/icspdat ra0 ttl cmos porta i/o with prog. pull-up and interrupt-on-change an0 an ? a/d channel 0 input c1in+ an ? comparator c1 non-inverting input icspdat st cmos serial programming data i/o ra1/an1/c12in0-/v ref /icspclk ra1 ttl cmos porta i/o with prog. pull-up and interrupt-on-change an1 an ? a/d channel 1 input c12in0- an ? comparators c1 and c2 inverting input v ref an ? external voltage reference for a/d icspclk st ? serial programming clock ra2/an2/t0cki/int/c1out ra2 st cmos porta i/o with prog. pull-up and interrupt-on-change an2 an ? a/d channel 2 input t0cki st ? timer0 clock input int st ? external interrupt c1out ? cmos comparator c1 output ra3/mclr /v pp ra3 ttl ? porta input with interrupt-on-change mclr st ? master clear w/internal pull-up v pp hv ? programming voltage ra4/an3/t1g /osc2/clkout ra4 ttl cmos porta i/o with prog. pull-up and interrupt-on-change an3 an ? a/d channel 3 input t1g st ? timer1 gate (count enable) osc2 ? xtal crystal/resonator clkout ? cmos f osc /4 output ra5/t1cki/osc1/clkin ra5 ttl cmos porta i/o with prog. pull-up and interrupt-on-change t1cki st ? timer1 clock input osc1 xtal ? crystal/resonator clkin st ? external clock input/rc oscillator connection rc0/an4/c2in+ rc0 ttl cmos portc i/o an4 an ? a/d channel 4 input c2in+ an ? comparator c2 non-inverting input rc1/an5/c12in1- rc1 ttl cmos portc i/o an5 an ? a/d channel 5 input c12in1- an ? comparators c1 and c2 inverting input rc2/an6/c12in2-/p1d rc2 ttl cmos portc i/o an6 an ? a/d channel 6 input c12in2- an ? comparators c1 and c2 inverting input p1d ? cmos pwm output rc3/an7/c12in3-/p1c rc3 ttl cmos portc i/o an7 an ? a/d channel 7 input c12in3- an ? comparators c1 and c2 inverting input p1c ? cmos pwm output rc4/c2out/p1b rc4 ttl cmos portc i/o c2out ? cmos comparator c2 output p1b ? cmos pwm output rc5/ccp1/p1a rc5 ttl cmos portc i/o ccp1 st cmos capture input/compare output p1a ? cmos pwm output v dd v dd power ? positive supply v ss v ss power ? ground reference legend: an = analog input or output cmos = cmos compatible input or output hv = high voltage st = schmitt trigger input with cmos levels ttl = ttl compatible input xtal = crystal
? 2007 microchip technology inc. preliminary ds41288c-page 11 pic16f610/616/16hv610/616 2.0 memory organization 2.1 program memory organization the pic16f610/616/16hv610/616 has a 13-bit pro- gram counter capable of addressing an 8k x 14 pro- gram memory space. only the first 1k x 14 (0000h-3ff) for the pic16f610/16hv610 and the first 2k x 14 (0000h-07ffh) for the PIC16F616/16hv616 is physically implemented. accessing a location above these boundaries will cause a wraparound within the first 1k x 14 space (pic16f610/16hv610) and 2k x 14 space (PIC16F616/16hv616). the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 2-1). figure 2-1: program memory map and stack for the pic16f610/16hv610 figure 2-2: program memory map and stack for the PIC16F616/16hv616 pc<12:0> 13 0000h 0004h 0005h 03ffh 0400h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2 pc<12:0> 13 0000h 0004h 0005h 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2
pic16f610/616/16hv610/616 ds41288c-page 12 preliminary ? 2007 microchip technology inc. 2.2 data memory organization the data memory (see figure 2-4) is partitioned into two banks, which contain the general purpose registers (gpr) and the special function registers (sfr). the special function registers are located in the first 32 locations of each bank. pic16f610/16hv610 register locations 40h-7fh in bank 0 are general purpose registers, implemented as static ram. PIC16F616/16hv616 register locations 20h-7fh in bank 0 and a0h-bfh in bank 1 are general purpose registers, implemented as static ram. register locations f0h-ffh in bank 1 point to addresses 70h-7fh in bank 0. all other ram is unimplemented and returns ? 0 ? when read. the rp0 bit of the status register is the bank select bit. rp0 0 bank 0 is selected 1 bank 1 is selected 2.2.1 general purpose register file the register file is organized as 64 x 8 in the pic16f610/16hv610 and 128 x 8 in the PIC16F616/16hv616. each register is accessed, either directly or indirectly, through the file select reg- ister (fsr) (see section 2.4 ?indirect addressing, indf and fsr registers? ). 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (see table 2-1). these registers are static ram. the special registers can be classified into two sets: core and peripheral. the special function registers associated with the ?core? are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. note: the irp and rp1 bits of the status register are reserved and should always be maintained as ? 0 ?s.
? 2007 microchip technology inc. preliminary ds41288c-page 13 pic16f610/616/16hv610/616 figure 2-3: data memory map of the pic16f610/16hv610 figure 2-4: data memory map of the PIC16F616/16hv616 indirect addr. (1) tmr0 pcl status fsr porta pclath intcon pir1 tmr1l tmr1h t1con 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 7fh bank 0 unimplemented data memory locations, read as ? 0 ?. note 1: not a physical register. cm1con0 srcon0 general purpose registers 64 bytes srcon1 file address file address wpua ioca indirect addr. (1) option_reg pcl status fsr trisa pclath intcon pie1 pcon 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh a0h ffh bank 1 ansel trisc portc accesses 70h-7fh f0h vrcon cm2con0 osctune cm2con1 3fh 40h indirect addr. (1) tmr0 pcl status fsr porta pclath intcon pir1 tmr1l tmr1h t1con 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 7fh bank 0 unimplemented data memory locations, read as ? 0 ?. note 1: not a physical register. cm1con0 srcon0 general purpose registers 96 bytes srcon1 file address file address wpua ioca indirect addr. (1) option_reg pcl status fsr trisa pclath intcon pie1 pcon 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh a0h ffh bank 1 adresh adcon0 adresl adcon1 ansel trisc portc bfh general purpose registers 32 bytes accesses 70h-7fh f0h tmr2 t2con ccpr1l ccpr1h ccp1con pwm1con eccpas vrcon cm2con0 osctune pr2 70h 6fh cm2con1 c0h
pic16f610/616/16hv610/616 ds41288c-page 14 preliminary ? 2007 microchip technology inc. table 2-1: pic16f610/616/16hv610/616 sp ecial function registers summary bank 0 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor page bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22, 113 01h tmr0 timer0 module?s register xxxx xxxx 43, 113 02h pcl program counter?s (pc) least significant byte 0000 0000 22, 113 03h status irp (1) rp1 (1) rp0 to pd zdcc 0001 1xxx 16, 113 04h fsr indirect data memory address pointer xxxx xxxx 22, 113 05h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 31, 113 06h ? unimplemented ? ? 07h portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx 00xx 40, 113 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 22, 113 0bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 18, 113 0ch pir1 ?adif (2) ccp1if (2) c2if c1if ?tmr2if (2) tmr1if -000 0-00 20, 113 0dh ? unimplemented ? ? 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx 47, 113 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx 47, 113 10h t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 50, 113 11h tmr2 (2) timer2 module register 0000 0000 53, 113 12h t2con (2) ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 54, 113 13h ccpr1l (2) capture/compare/pwm register 1 low byte xxxx xxxx 84, 113 14h ccpr1h (2) capture/compare/pwm register 1 high byte xxxx xxxx 84, 113 15h ccp1con (2) p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 83, 113 16h pwm1con (2) prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 0000 0000 83, 113 17h eccpas (2) eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 100, 113 18h ? unimplemented ? ? 19h vrcon c1vren c2vren vrr fvren vr3 vr2 vr1 vr0 0000 0000 70, 113 1ah cm1con0 c1on c1out c1oe c1pol ? c1r c1ch1 c1ch0 0000 -000 60, 113 1bh cm2con0 c2on c2out c2oe c2pol ? c2r c2ch1 c2ch0 0000 -000 61, 113 1ch cm2con1 mc1out mc2out ? t1acs c1hys c2hys t1gss c2sync 00-0 0010 63, 113 1dh ? unimplemented ? ? 1eh adresh (2) most significant 8 bits of the left shifted a/d result or 2 bits of right shifted result xxxx xxxx 78, 113 1fh adcon0 (2) adfm vcfg chs3 chs2 chs1 chs0 go/done adon 0000 0000 76, 113 legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: irp and rp1 bits are reserved, always maintain these bits clear. 2: PIC16F616/16hv616 only.
? 2007 microchip technology inc. preliminary ds41288c-page 15 pic16f610/616/16hv610/616 table 2-2: pic16f610/616/16hv610/616 special function registers summary bank 1 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor page bank 1 80h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22, 113 81h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 17, 113 82h pcl program counter?s (pc) least significant byte 0000 0000 22, 113 83h status irp (1) rp1 (1) rp0 to pd zdcc 0001 1xxx 16, 113 84h fsr indirect data memory address pointer xxxx xxxx 22, 113 85h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 31, 113 86h ? unimplemented ? ? 87h trisc ? ? trisc5 trisc4 trisc3 t risc2 trisc1 trisc0 --11 1111 40, 113 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 22, 113 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 18, 113 8ch pie1 ?adie (3) ccp1ie (3) c2ie c1ie ?tmr2ie (3) tmr1ie -000 0-00 19, 113 8dh ? unimplemented ? ? 8eh pcon ? ? ? ? ? ?por bor ---- --qq 21, 113 8fh ? unimplemented ? ? 90h osctune ? ? ? tun4 tun3 tun2 tun1 tun0 ---0 0000 29, 113 91h ansel ans7 ans6 ans5 ans4 ans3 (3) ans2 (3) ans1 ans0 1111 1111 32, 114 92h pr2 (3) timer2 module period register 1111 1111 53, 114 93h ? unimplemented ? ? 94h ? unimplemented ? ? 95h wpua ? ? wpua5 wpua4 ? wpua2 wpua1 wpua0 --11 -111 33, 114 96h ioca ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 --00 0000 33, 114 97h ? unimplemented ? ? 98h ? unimplemented ? ? 99h srcon0 sr1 sr0 c1sen c2ren pulss pulsr ? srclken 0000 00-0 67, 114 9ah srcon1 srcs1 srcs0 ? ? ? ? ? ? 00-- ---- 67, 114 9bh ? unimplemented ? ? 9ch ? unimplemented ? ? 9dh ? unimplemented ? ? 9eh adresl (3) least significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 78, 114 9fh adcon1 (3) ? adcs2 adcs1 adcs0 ? ? ? ? -000 ---- 77, 114 legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: irp and rp1 bits are reserved, always maintain these bits clear. 2: ra3 pull-up is enabled when mclre is ? 1 ? in the configuration word register. 3: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 16 preliminary ? 2007 microchip technology inc. 2.2.2.1 status register the status register, shown in register 2-1, contains: ? the arithmetic status of the alu ? the reset status ? the bank select bits for data memory (ram) the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status, will clear the upper three bits and set the z bit. this leaves the status register as ?000u u1uu? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affect- ing any status bits, see the section 13.0 ?instruction set summary? . note 1: bits irp and rp1 of the status register are not used by the pic16f610/616/16hv610/616 and should be maintained as clear. use of these bits is not recommended, since this may affect upward compatibility with future products. 2: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. register 2-1: status: status register reserved reserved r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 irp: this bit is reserved and should be maintained as ? 0 ? bit 6 rp1: this bit is reserved and should be maintained as ? 0 ? bit 5 rp0: register bank select bit (used for direct addressing) 1 = bank 1 (80h ? ffh) 0 = bank 0 (00h ? 7fh) bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions), for borrow , the polarity is reversed. 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw, sublw, subwf instructions) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the hi gh-order or low-order bit of the source register.
? 2007 microchip technology inc. preliminary ds41288c-page 17 pic16f610/616/16hv610/616 2.2.2.2 option register the option register is a readable and writable regis- ter, which contains various control bits to configure: ? timer0/wdt prescaler ? external ra2/int interrupt ?timer0 ? weak pull-ups on porta note: to achieve a 1:1 prescaler assignment for timer0, assign the prescaler to the wdt by setting psa bit to ? 1 ? of the option register. see section 5.1.3 ?software programmable prescaler? . register 2-2: option_reg: option register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rapu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rapu : porta pull-up enable bit 1 = porta pull-ups are disabled 0 = porta pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of ra2/int pin 0 = interrupt on falling edge of ra2/int pin bit 5 t0cs: timer0 clock source select bit 1 = transition on ra2/t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 t0se: timer0 source edge select bit 1 = increment on high-to-low transition on ra2/t0cki pin 0 = increment on low-to-high transition on ra2/t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
pic16f610/616/16hv610/616 ds41288c-page 18 preliminary ? 2007 microchip technology inc. 2.2.2.3 intcon register the intcon register is a readable and writable register, which contains the various enable and flag bits for tmr0 register overflow, porta change and external ra2/int pin interrupts. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 2-3: intcon: interrupt control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gie peie t0ie inte raie t0if intf raif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: ra2/int external interrupt enable bit 1 = enables the ra2/int external interrupt 0 = disables the ra2/int external interrupt bit 3 raie: porta change interrupt enable bit (1) 1 = enables the porta change interrupt 0 = disables the porta change interrupt bit 2 t0if: timer0 overflow interrupt flag bit (2) 1 = timer0 register has overflowed (must be cleared in software) 0 = timer0 register did not overflow bit 1 intf: ra2/int external interrupt flag bit 1 = the ra2/int external interrupt occurred (must be cleared in software) 0 = the ra2/int external interrupt did not occur bit 0 raif: porta change interrupt flag bit 1 = when at least one of the porta <5:0> pins changed state (must be cleared in software) 0 = none of the porta <5:0> pins have changed state note 1: ioca register must also be enabled. 2: t0if bit is set when tmr0 rolls over. tmr0 is unchanged on reset and should be initialized before clearing t0if bit.
? 2007 microchip technology inc. preliminary ds41288c-page 19 pic16f610/616/16hv610/616 2.2.2.4 pie1 register the pie1 register contains the peripheral interrupt enable bits, as shown in register 2-4. note: bit peie of the intcon register must be set to enable any peripheral interrupt. register 2-4: pie1: peripheral interrupt enable register 1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ?adie (1) ccp1ie (1) c2ie c1ie ?tmr2ie (1) tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 adie: a/d converter (adc) interrupt enable bit (1) 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 ccp1ie: ccp1 interrupt enable bit (1) 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 4 c2ie: comparator c2 interrupt enable bit 1 = enables the comparator c2 interrupt 0 = disables the comparator c2 interrupt bit 3 c1ie: comparator c1 interrupt enable bit 1 = enables the comparator c1 interrupt 0 = disables the comparator c1 interrupt bit 2 unimplemented: read as ? 0 ? bit 1 tmr2ie: timer2 to pr2 match interrupt enable bit (1) 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt note 1: PIC16F616/16hv616 only. pic16f610/16hv610 unimplemented, read as ? 0 ?.
pic16f610/616/16hv610/616 ds41288c-page 20 preliminary ? 2007 microchip technology inc. 2.2.2.5 pir1 register the pir1 register contains the peripheral interrupt flag bits, as shown in register 2-5. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 2-5: pir1: peripheral interrupt request register 1 u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ?adif (1) ccp1if (1) c2if c1if ?tmr2if (1) tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 adif: a/d interrupt flag bit (1) 1 = a/d conversion complete 0 = a/d conversion has not completed or has not been started bit 5 ccp1if: ccp1 interrupt flag bit (1) capture mod e: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode : 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode : unused in this mode bit 4 c2if: comparator c2 interrupt flag bit 1 = comparator c2 output has changed (must be cleared in software) 0 = comparator c2 output has not changed bit 3 c1if: comparator c1 interrupt flag bit 1 = comparator c1 output has changed (must be cleared in software) 0 = comparator c1 output has not changed bit 2 unimplemented: read as ? 0 ? bit 1 tmr2if: timer2 to pr2 match interrupt flag bit (1) 1 = timer2 to pr2 match occurred (must be cleared in software) 0 = timer2 to pr2 match has not occurred bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = timer1 register overflowed (must be cleared in software) 0 = timer1 has not overflowed note 1: PIC16F616/16hv616 only. pic16f610/16hv610 unimplemented, read as ? 0 ?.
? 2007 microchip technology inc. preliminary ds41288c-page 21 pic16f610/616/16hv610/616 2.2.2.6 pcon register the power control (pcon) register (see table 12-2) contains flag bits to differentiate between a: ? power-on reset (por ) ? brown-out reset (bor ) ? watchdog timer reset (wdt) ? external mclr reset the pcon register also controls the software enable of the bor . the pcon register bits are shown in register 2-6. register 2-6: pcon: power control register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 (1) ? ? ? ? ? ?por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: reads as ? 0 ? if brown-out reset is disabled.
pic16f610/616/16hv610/616 ds41288c-page 22 preliminary ? 2007 microchip technology inc. 2.3 pcl and pclath the program counter (pc) is 13 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 2-5 shows the two situations for the loading of the pc. the upper example in figure 2-5 shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in figure 2-5 shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). figure 2-5: loading of pc in different situations 2.3.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<12:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the pclath register. when the lower 8 bits are written to the pcl register, all 13 bits of the program counter will change to the values contained in the pclath register and those being written to the pcl register. a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). care should be exercised when jumping into a look-up table or program branch table (computed goto ) by modifying the pcl register. assuming that pclath is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xff to 0x00 in the middle of the table, then pclath must be incremented for each address rollover that occurs between the table beginning and the target location within the table. for more information refer to application note an556, ? implementing a table read ? (ds00556). 2.3.2 stack the pic16f610/616/16hv610/616 family has an 8-level x 13-bit wide hardware stack (see figure 2-1). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 2.4 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actually accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr and the irp bit of the status register, as shown in figure 2-7. a simple program to clear ram location 40h-4fh using indirect addressing is shown in example 2-1. example 2-1: indirect addressing pc 12 8 7 0 5 pclath<4:0> pclath instruction wit h alu result goto, call opcode <10:0 > 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl a s destinatio n note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions or the vectoring to an interrupt address. movlw 0x40 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr, f ;inc pointer btfss fsr,4 ;all done? goto next ;no clear next continue ;yes continue
? 2007 microchip technology inc. preliminary ds41288c-page 23 pic16f610/616/16hv610/616 figure 2-6: direct/indirect addressing pic16f610/16hv610 figure 2-7: direct/indirect addressing PIC16F616/16hv616 data memory indirect addressing direct addressing bank select location select rp1 (1) rp0 6 0 from opcode irp (1) file select register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used (2) for memory map detail, see figure 2-3. 70h 40h unimplemented data memory locations, read as ? 0 ?. note 1: the rp1 and irp bits are reserved; always maintain these bits clear. 2: accesses in bank 2 and bank 3 are mirrored back into bank 0 and bank 1, respectively. 20h data memory indirect addressing direct addressing bank select location select rp1 (1) rp0 6 0 from opcode irp (1) file select register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used (2) for memory map detail, see figure 2-4. 70h 40h unimplemented data memory locations, read as ? 0 ?. note 1: the rp1 and irp bits are reserved; always maintain these bits clear. 2: accesses in bank 2 and bank 3 are mirrored back into bank 0 and bank 1, respectively.
pic16f610/616/16hv610/616 ds41288c-page 24 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 25 pic16f610/616/16hv610/616 3.0 oscillator module 3.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 3-1 illustrates a block diagram of the oscillator module. clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system clock source can be configured with a choice of two selectable speeds: internal or external system clock source. the oscillator module can be configured in one of eight clock modes. 1. ec ? external clock with i/o on osc2/clkout. 2. lp ? 32 khz low-power crystal mode. 3. xt ? medium gain crystal or ceramic resonator oscillator mode. 4. hs ? high gain crystal or ceramic resonator mode. 5. rc ? external resistor-capacitor (rc) with f osc /4 output on osc2/clkout. 6. rcio ? external resistor-capacitor (rc) with i/o on osc2/clkout. 7. intosc ? internal oscillator with f osc /4 output on osc2 and i/o on osc1/clkin. 8. intoscio ? internal oscillator with i/o on osc1/clkin and osc2/clkout. clock source modes are configured by the fosc<2:0> bits in the configuration word register (config). the internal oscillator module provides a selectable system clock mode of either 4 mhz (postscaler) or 8 mhz (intosc). figure 3-1: pic ? mcu clock source block diagram (cpu and peripherals) osc1 osc2 sleep external oscillator lp, xt, hs, rc, rcio, ec system clock mux fosc<2:0> (configuration word register) internal oscillator intosc 8 mhz postscaler 4 mhz intosc ioscfs
pic16f610/616/16hv610/616 ds41288c-page 26 preliminary ? 2007 microchip technology inc. 3.2 clock source modes clock source modes can be classified as external or internal. ? external clock modes rely on external circuitry for the clock source. examples are: oscillator mod- ules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt and hs modes) and resistor-capacitor (rc) mode circuits. ? internal clock sources are contained internally within the oscillator module. the oscillator module has two selectable clock frequencies: 4 mhz and 8 mhz the system clock can be selected between external or internal clock sources via the fosc<2:0> bits of the configuration word register. 3.3 external clock modes 3.3.1 ec mode the external clock (ec) mode allows an externally generated logic level as the system clock source. when operating in this mode, an external clock source is connected to the osc1 input and the osc2 is available for general purpose i/o. figure 3-2 shows the pin connections for ec mode. the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 3-2: external clock (ec) mode operation 3.3.2 oscillator start-up timer (ost) if the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations from osc1. this occurs following a power-on reset (por) and when the power-up timer (pwrt) has expired (if configured), or a wake-up from sleep. during this time, the program counter does not increment and program execution is suspended. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscillator delays are shown in table 3-1. table 3-1: oscillator delay examples osc1/clkin osc2/clkout (1) i/o clock from ext. system pic ? mcu note 1: alternate pin functions are listed in the section 1.0 ?device overview? . switch from switch to frequency oscillator delay sleep/por intosc 4 mhz to 8 mhz oscillator warm-up delay (t warm ) sleep/por ec, rc dc ? 20 mhz 2 instruction cycles sleep/por lp, xt, hs 32 khz to 20 mhz 1024 clock cycles (ost)
? 2007 microchip technology inc. preliminary ds41288c-page 27 pic16f610/616/16hv610/616 3.3.3 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 (figure 3-3). the mode selects a low, medium or high gain setting of the internal inverter- amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is designed to drive only 32.768 khz tuning-fork type crystals (watch crystals). xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current consumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting. figure 3-3 and figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively. figure 3-3: quartz crystal operation (lp, xt or hs mode) figure 3-4: ceramic resonator operation (xt or hs mode) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m to 10 m ) . c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clkout note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m to 10 m ) . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clkout
pic16f610/616/16hv610/616 ds41288c-page 28 preliminary ? 2007 microchip technology inc. 3.3.4 external rc modes the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. there are two modes: rc and rcio. in rc mode, the rc circuit connects to osc1. osc2/ clkout outputs the rc oscillator frequency divided by 4. this signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. figure 3-5 shows the external rc mode connections. figure 3-5: external rc modes in rcio mode, the rc circuit is connected to osc1. osc2 becomes an additional general purpose i/o pin. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. other factors affecting the oscillator frequency are: ? threshold voltage variation ? component tolerances ? packaging variations in capacitance the user also needs to take into account variation due to tolerance of external rc components used. 3.4 internal clock modes the oscillator module provides a selectable system clock source of either 4 mhz or 8 mhz. the selectable frequency is configured through the ioscfs bit of the configuration word. the frequency of the internal oscillator can be can be user-adjusted via software using the osctune register. 3.4.1 intosc and intoscio modes the intosc and intoscio modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the fosc<2:0> bits in the configuration word register (config). see section 12.0 ?special features of the cpu? for more information. in intosc mode, osc1/clkin is available for general purpose i/o. osc2/clkout outputs the selected internal oscillator frequency divided by 4. the clkout signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. in intoscio mode, osc1/clkin and osc2/clkout are available for general purpose i/o. osc2/clkout (1) c ext r ext pic ? mcu osc1/clkin f osc /4 or internal clock v dd v ss recommended values: 10 k r ext 100 k , <3v 3 k r ext 100 k , 3-5v c ext > 20 pf, 2-5v note 1: alternate pin functions are listed in section 1.0 ?device overview? . 2: output depends upon rc or rcio clock mode. i/o (2)
? 2007 microchip technology inc. preliminary ds41288c-page 29 pic16f610/616/16hv610/616 3.4.1.1 osctune register the oscillator is factory calibrated but can be adjusted in software by writing to the osctune register (register 3-1). the default value of the osctune register is ? 0 ?. the value is a 5-bit two?s complement number. when the osctune register is modified, the frequency will begin shifting to the new frequency. code execution continues during this shift. there is no indication that the shift has occurred. table 3-2: summary of registers associated with clock sources register 3-1: osctune: oscillator tuning register u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4-0 tun<4:0>: frequency tuning bits 01111 = maximum frequency 01110 = ? ? ? 00001 = 00000 = oscillator module is running at the manufacturer calibrated frequency. 11111 = ? ? ? 10000 = minimum frequency name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (1) config (2) ioscfs cp mclre pwrte wdte fosc2 fosc1 fosc0 ? ? osctune ? ? ? tun4 tun3 tun2 tun1 tun0 ---0 0000 ---u uuuu legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by oscillators. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: see configuration word register (register 12-1) for operation of all register bits.
pic16f610/616/16hv610/616 ds41288c-page 30 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 31 pic16f610/616/16hv610/616 4.0 i/o ports there are as many as eleven general purpose i/o pins and an input pin available. depending on which peripherals are enabled, some or all of the pins may not be available as general purpose i/o. in general, when a peripheral is enabled, the associated pin may not be used as a general purpose i/o pin. 4.1 porta and the trisa registers porta is a 6-bit wide, bidirectional port. the corresponding data direction register is trisa (register 4-2). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). the exception is ra3, which is input only and its tris bit will always read as ? 1 ?. example 4-1 shows how to initialize porta. reading the porta register (register 4-1) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. ra3 reads ? 0 ? when mclre = 1 . the trisa register controls the direction of the porta pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 4-1: initializing porta note: the ansel register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ? and cannot generate an interrupt. bcf status,rp0 ;bank 0 clrf porta ;init porta bsf status,rp0 ;bank 1 clrf ansel ;digital i/o movlw 0ch ;set ra<3:2> as inputs movwf trisa ;and set ra<5:4,1:0> ;as outputs bcf status,rp0 ;bank 0 register 4-1: porta: porta register u-0 u-0 r/w-x r/w-0 r-x r/w-0 r/w-0 r/w-0 ? ? ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented : read as ? 0 ? bit 5-0 ra<5:0> : porta i/o pin bit 1 = porta pin is > v ih 0 = porta pin is < v il register 4-2: trisa: porta tri-state register u-0 u-0 r/w-1 r/w-1 r-1 r/w-1 r/w-1 r/w-1 ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented : read as ? 0 ? bit 5-0 trisa<5:0>: porta tri-state control bit 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output note 1: trisa<3> always reads ? 1 ?. 2: trisa<5:4> always reads ? 1 ? in xt, hs and lp oscillator modes.
pic16f610/616/16hv610/616 ds41288c-page 32 preliminary ? 2007 microchip technology inc. 4.2 additional pin functions every porta pin on the pic16f610/616/16hv610/ 616 has an interrupt-on-change option and a weak pull- up option. the next three sections describe these functions. 4.2.1 ansel register the ansel register is used to configure the input mode of an i/o pin to analog. setting the appropriate ansel bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansel bits has no affect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 4.2.2 weak pull-ups each of the porta pins, except ra3, has an individually configurable internal weak pull-up. control bits wpuax enable or disable each pull-up. refer to register 4-4. each weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset by the rapu bit of the option register). a weak pull-up is automatically enabled for ra3 when configured as mclr and disabled when ra3 is an i/o. there is no software control of the mclr pull-up. 4.2.3 interrupt-on-change each porta pin is individually configurable as an interrupt-on-change pin. control bits iocax enable or disable the interrupt function for each pin. refer to register 4-5. the interrupt-on-change is disabled on a power-on reset. for enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of porta. the ?mismatch? outputs of the last read are or?d together to set the porta change interrupt flag bit (raif) in the intcon register (register 2-3). this interrupt can wake the device from sleep. the user, in the interrupt service routine, clears the interrupt by: a) any read or write of porta. this will end the mismatch condition, then, b) clear the flag bit raif. a mismatch condition will continue to set flag bit raif. reading porta will end the mismatch condition and allow flag bit raif to be cleared. the latch holding the last read value is not affected by a mclr nor bor reset. after these resets, the raif flag will continue to be set if a mismatch is present. note: if a change on the i/o pin should occur when any porta operation is being executed, then the raif interrupt flag may not get set. register 4-3: ansel: analog select register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ans<7:0> : analog select bits analog select between analog or digital function on pins an<7:0>, respectively. 1 = analog input. pin is assigned as analog input (1) . 0 = digital i/o. pin is assigned to port or special function. note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
? 2007 microchip technology inc. preliminary ds41288c-page 33 pic16f610/616/16hv610/616 register 4-4: wpua: weak pull-up porta register u-0 u-0 r/w-1 r/w-1 u-0 r/w-1 r/w-1 r/w-1 ? ? wpua5 wpua4 ? wpua2 wpua1 wpua0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented : read as ? 0 ? bit 5-4 wpua<5:4>: weak pull-up control bits 1 = pull-up enabled 0 = pull-up disabled bit 3 unimplemented : read as ? 0 ? bit 2-0 wpua<2:0>: weak pull-up control bits 1 = pull-up enabled 0 = pull-up disabled note 1: global rapu must be enabled for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in output mode (trisa = 0 ). 3: the ra3 pull-up is enabled when configured as mclr and disabled as an input in the configuration word. 4: wpua<5:4> always reads ? 1 ? in xt, hs and lp oscillator modes. register 4-5: ioca: interrupt-on-change porta register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented : read as ? 0 ? bit 5-0 ioca<5:0>: interrupt-on-change porta control bit 1 = interrupt-on-change enabled 0 = interrupt-on-change disabled note 1: global interrupt enable (gie) must be enabled for individual interrupts to be recognized. 2: ioca<5:4> always reads ? 1 ? in xt, hs and lp oscillator modes.
pic16f610/616/16hv610/616 ds41288c-page 34 preliminary ? 2007 microchip technology inc. 4.2.4 pin descriptions and diagrams each porta pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individual functions such as the comparator or the adc, refer to the appropriate section in this data sheet. 4.2.4.1 ra0/an0 (1) /c1in+/icspdat figure 4-1 shows the diagram for this pin. the ra0 pin is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? an analog non-inverting input to the comparator ? in-circuit serial programming data 4.2.4.2 ra1/an1 (1) /c12in0-/v ref (1) / icspclk figure 4-1 shows the diagram for this pin. the ra1 pin is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? an analog inverting input to the comparator ? a voltage reference input for the adc (1) ? in-circuit serial programming clock figure 4-1: block diagram of ra<1:0> note 1: PIC16F616/16hv616 only. v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak rd porta rd wr wr rd wr ioca rd ioca interrupt-on- to comparator analog (1) input mode rap u analog (1) input mode change q1 wr rd wpua data bus wpua porta trisa trisa porta note 1: comparator mode and ansel determines analog input mode. 2: set has priority over reset. 3: PIC16F616/16hv616 only. to a/d converter (3) i/o pin s (2) r q from other ra<5:1> pins (ra0) write ? 0 ? to raif ra<5:2, 0> pins (ra1)
? 2007 microchip technology inc. preliminary ds41288c-page 35 pic16f610/616/16hv610/616 4.2.4.3 ra2/an2 (1) /t0cki/int/c1out figure 4-2 shows the diagram for this pin. the ra2 pin is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? the clock input for tmr0 ? an external edge triggered interrupt ? a digital output from comparator c1 figure 4-2: block diagram of ra2 note 1: PIC16F616/16hv616 only. v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak rd porta rd wr wr rd wr ioac rd ioac interrupt-on- to int analog (1) input mode rap u analog (1) input mode change q1 wr rd wpua data bus wpua porta trisa trisa porta note 1: comparator mode and ansel determines analog input mode. 2: set has priority over reset. 3: PIC16F616/16hv616 only. to a/d converter (3) i/o pin s (2) r q from other ra<5:3, 1:0> pins write ? 0 ? to raif 0 1 c1oe c1oe enable to timer0
pic16f610/616/16hv610/616 ds41288c-page 36 preliminary ? 2007 microchip technology inc. 4.2.4.4 ra3/mclr /v pp figure 4-3 shows the diagram for this pin. the ra3 pin is configurable to function as one of the following: ? a general purpose input ? as master clear reset with weak pull-up figure 4-3: block diagram of ra3 v ss d q ck q d en q data bus rd porta rd porta wr ioca rd ioca reset mclre rd trisa v ss d en q mclre v dd weak mclre q1 input pin interrupt-on- change s (1) r q from other write ? 0 ? to raif note 1: set has priority over reset ra<5:4, 2:0> pins
? 2007 microchip technology inc. preliminary ds41288c-page 37 pic16f610/616/16hv610/616 4.2.4.5 ra4/an3 (1) /t1g /osc2/clkout figure 4-4 shows the diagram for this pin. the ra4 pin is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? a timer1 gate (count enable) ? a crystal/resonator connection ? a clock output figure 4-4: block diagram of ra4 note 1: PIC16F616/16hv616 only. v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak analog input mode data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca f osc /4 to a/d converter (5) oscillator circuit osc1 clkout 0 1 clkout enable enable analog (3) input mode rap u rd porta to t 1 g intosc/ rc/ec (2) clk (1) modes clkout enable note 1: clk modes are xt, hs, lp, tmr1 lp and clkout enable. 2: with clkout option. 3: analog input mode comes from ansel. 4: set has priority over reset. 5: PIC16F616/16hv616 only. q1 i/o pin interrupt-on- change s (4) r q from other write ? 0 ? to raif ra<5, 3:0> pins
pic16f610/616/16hv610/616 ds41288c-page 38 preliminary ? 2007 microchip technology inc. 4.2.4.6 ra5/t1cki/osc1/clkin figure 4-5 shows the diagram for this pin. the ra5 pin is configurable to function as one of the following: ? a general purpose i/o ? a timer1 clock input ? a crystal/resonator connection ? a clock input figure 4-5: block diagram of ra5 v dd v ss d q ck q d q ck q d q ck q d q ck q v dd d en q d en q weak data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca to ti m e r1 intosc mode rd porta intosc mode rap u osc2 note 1: timer1 lp oscillator enabled. 2: set has priority over reset. tmr1lpen (1) oscillator circuit q1 i/o pin interrupt-on- change s (2) r q from other ra<4:0> pins write ? 0 ? to raif
? 2007 microchip technology inc. preliminary ds41288c-page 39 pic16f610/616/16hv610/616 table 4-1: summary of registers associated with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 cm1con0 c1on c1out c1oe c1pol ? c1r c1ch1 c1ch0 0000 -000 0000 -000 cm2con0 c2on c2out c2oe c2pol ? c2r c2ch1 c2ch0 0000 -000 0000 -000 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 ioca ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 --00 0000 --00 0000 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 --u0 u000 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 wpua ? ?wpua5wpua4 ? wpua2 wpua1 wpua0 --11 -111 --11 -111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta.
pic16f610/616/16hv610/616 ds41288c-page 40 preliminary ? 2007 microchip technology inc. 4.3 portc and the trisc registers portc is a general purpose i/o port consisting of 6 bidirectional pins. the pins can be configured for either digital i/o or analog input to a/d converter (adc) or comparator. for specific information about individual functions such as the enhanced ccp or the adc, refer to the appropriate section in this data sheet. example 4-2: initializing portc note: the ansel register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ? and cannot generate an interrupt. bcf status,rp0 ;bank 0 clrf portc ;init portc bsf status,rp0 ;bank 1 clrf ansel ;digital i/o movlw 0ch ;set rc<3:2> as inputs movwf trisc ;and set rc<5:4,1:0> ;as outputs bcf status,rp0 ;bank 0 register 4-6: portc: portc register u-0 u-0 r/w-x r/w-x r/w-0 r/w-0 r/w-x r/w-x ? ? rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented : read as ? 0 ? bit 5-0 rc<5:0> : portc i/o pin bit 1 = portc pin is > v ih 0 = portc pin is < v il register 4-7: trisc: portc tri-state register u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented : read as ? 0 ? bit 5-0 trisc<5:0>: portc tri-state control bit 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output
? 2007 microchip technology inc. preliminary ds41288c-page 41 pic16f610/616/16hv610/616 4.3.1 rc0/an4 (1) /c2in+ the rc0 is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? an analog non-inverting input to comparator c2 4.3.2 rc1/an5 (1) /c12in1- the rc1 is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? an analog inverting input to the comparator figure 4-6: block diagram of rc0 and rc1 4.3.3 rc2/an6 (1) /c12in2-/p1d (1) the rc2 is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? an analog input to comparators c1 and c2 ? a digital output from the enhanced ccp (1) 4.3.4 rc3/an7 (1) /c12in3-/p1c (1) the rc3 is configurable to function as one of the following: ? a general purpose i/o ? an analog input for the adc (1) ? an analog inverting input to comparators c1 and c2 ? a digital output from the enhanced ccp (1) figure 4-7: block diagram of rc2 and rc3 note 1: PIC16F616/16hv616 only. i/o pi n v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a/d converter rd portc analog input mode (1) to comparators note 1: analog input mode comes from ansel or comparator mode. note 1: PIC16F616/16hv616 only. i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a/d converter rd portc analog input mode (1) 0 1 ccpout ccpout (2) enable note 1: analog input mode comes from ansel. 2: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 42 preliminary ? 2007 microchip technology inc. 4.3.5 rc4/c2out/p1b (1) the rc4 is configurable to function as one of the following: ? a general purpose i/o ? a digital output from comparator c2 ? a digital output from the enhanced ccp (1) figure 4-8: block diagram of rc4 4.3.6 rc5/ccp1 (1) /p1a (1) the rc5 is configurable to function as one of the following: ? a general purpose i/o ? a digital input/output for the enhanced ccp (1) figure 4-9: block diagram of rc5 pin table 4-2: summary of registers associated with portc note 1: PIC16F616/16hv616 only. 2: enabling both c2out and p1b will cause a conflict on rc4 and create unpredictable results. therefore, if c2out is enabled, the eccp can not be used in half-bridge or full-bridge mode and vice-versa. i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc rd portc 0 1 note 1: port/peripheral select signals selects between port data and peripheral output. c2oe ccp1m<3:0> c2oe c2out ccp1m<3:0> ccpout/p1b note 1: PIC16F616/16hv616 only. i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to enhanced ccp rd portc 0 1 ccp1out (1) / ccp1out (1) enable p1a note 1: PIC16F616/16hv616 only. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 cm1con0 c1on c1out c1oe c1pol ? c1r c1ch1 c1ch0 0000 -000 0000 -000 cm2con0 c2on c2out c2oe c2pol ? c2r c2ch1 c2ch0 0000 -000 0000 -000 portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx 00xx --uu 00uu trisc ? ? trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portc.
? 2007 microchip technology inc. preliminary ds41288c-page 43 pic16f610/616/16hv610/616 5.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 8-bit prescaler (shared with watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow figure 5-1 is a block diagram of the timer0 module. 5.1 timer0 operation when used as a timer, the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 5.1.1 8-bit timer mode when used as a timer, the timer0 module will increment every instruction cycle (without prescaler). timer mode is selected by clearing the t0cs bit of the option register to ? 0 ?. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 5.1.2 8-bit counter mode when used as a counter, the timer0 module will increment on every rising or falling edge of the t0cki pin. the incrementing edge is determined by the t0se bit of the option register. counter mode is selected by setting the t0cs bit of the option register to ? 1 ?. figure 5-1: block diagram of the timer0/wdt prescaler note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. t0cki t0se pin tmr0 watchdog timer wdt time-out ps<2:0> wdte data bus set flag bit t0if on overflow t0cs note 1: t0se, t0cs, psa, ps<2:0> are bits in the option register. 2: wdte bit is in the configuration word register. 0 1 0 1 0 1 sync 2 tcy 8 8 8-bit prescaler 0 1 f osc /4 psa psa psa 3
pic16f610/616/16hv610/616 ds41288c-page 44 preliminary ? 2007 microchip technology inc. 5.1.3 software programmable prescaler a single software programmable prescaler is available for use with either timer0 or the watchdog timer (wdt), but not both simultaneously. the prescaler assignment is controlled by the psa bit of the option register. to assign the prescaler to timer0, the psa bit must be cleared to a ? 0 ?. there are 8 prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be assigned to the wdt module. the prescaler is not readable or writable. when assigned to the timer0 module, all instructions writing to the tmr0 register will clear the prescaler. when the prescaler is assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. 5.1.3.1 switching prescaler between timer0 and wdt modules as a result of having the prescaler assigned to either timer0 or the wdt, it is possible to generate an unintended device reset when switching prescaler values. when changing the prescaler assignment from timer0 to the wdt module, the instruction sequence shown in example 5-1 must be executed. example 5-1: changing prescaler (timer0 wdt) when changing the prescaler assignment from the wdt to the timer0 module, the following instruction sequence must be executed (see example 5-2). example 5-2: changing prescaler (wdt timer0) 5.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the t0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the t0if bit must be cleared in software. the timer0 interrupt enable is the t0ie bit of the intcon register. 5.1.5 using timer0 with an external clock when timer0 is in counter mode, the synchronization of the t0cki input and the timer0 register is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, the high and low periods of the external clock source must meet the timing requirements as shown in section 15.0 ?electrical specifications? . banksel tmr0 ; clrwdt ;clear wdt clrf tmr0 ;clear tmr0 and ;prescaler banksel option_reg ; bsf option_reg,psa ;select wdt clrwdt ; ; movlw b?11111000? ;mask prescaler andwf option_reg,w ;bits iorlw b?00000101? ;set wdt prescaler movwf option_reg ;to 1:32 note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep. clrwdt ;clear wdt and ;prescaler banksel option_reg ; movlw b?11110000? ;mask tmr0 select and andwf option_reg,w ;prescaler bits iorlw b?00000011? ;set prescale to 1:16 movwf option_reg ;
? 2007 microchip technology inc. preliminary ds41288c-page 45 pic16f610/616/16hv610/616 table 5-1: summary of registers associated with timer0 register 5-1: option_reg: option register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rapu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rapu : porta pull-up enable bit 1 = porta pull-ups are disabled 0 = porta pull-ups are enabled by individual port latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 t0cs: tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0 timer0 modules register xxxx xxxx uuuu uuuu intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the timer0 module.
pic16f610/616/16hv610/616 ds41288c-page 46 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 47 pic16f610/616/16hv610/616 6.0 timer1 module with gate control the timer1 module is a 16-bit timer/counter with the following features: ? 16-bit timer/counter register pair (tmr1h:tmr1l) ? programmable internal or external clock source ? 3-bit prescaler ? optional lp oscillator ? synchronous or asynchronous operation ? timer1 gate (count enable) via comparator or t1g pin ? interrupt on overflow ? wake-up on overflow (external clock, asynchronous mode only) ? time base for the capture/compare function ? special event trigger (with eccp) ? comparator output synchronization to timer1 clock figure 6-1 is a block diagram of the timer1 module. 6.1 timer1 operation the timer1 module is a 16-bit incrementing counter which is accessed through the tmr1h:tmr1l register pair. writes to tmr1h or tmr1l directly update the counter. when used with an internal clock source, the module is a timer. when used with an external clock source, the module can be used as either a timer or counter. 6.2 clock source selection the tmr1cs bit of the t1con register is used to select the clock source. when tmr1cs = 0 , the clock source is f osc /4. when tmr1cs = 1 , the clock source is supplied externally. figure 6-1: timer1 block diagram clock source tmr1cs t1acs f osc /4 00 f osc 01 t1cki pin 1x tmr1h tmr1l oscillator t1sync t1ckps<1:0> f osc /4 internal clock prescaler 1, 2, 4, 8 1 0 0 1 synchronized clock input 2 set flag bit tmr1if on overflow tmr1 (2) tmr1ge tmr1on t1oscen 1 0 c2out t1gss t1ginv to c2 comparator module timer1 clock tmr1cs osc2/t1g osc1/t1cki note 1: st buffer is low power type when using lp osc, or high speed type when using t1cki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep. (1) en intosc without clkout 1 0 t1acs f osc synchronize (3) det
pic16f610/616/16hv610/616 ds41288c-page 48 preliminary ? 2007 microchip technology inc. 6.2.1 internal clock source when the internal clock source is selected the tmr1h:tmr1l register pair will increment on multiples of t cy as determined by the timer1 prescaler. 6.2.2 external clock source when the external clock source is selected, the timer1 module may work as a timer or a counter. when counting, timer1 is incremented on the rising edge of the external clock input t1cki. in addition, the counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. if an external clock oscillator is needed (and the microcontroller is using the intosc without clkout), timer1 can use the lp oscillator as a clock source. 6.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits of the t1con register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 6.4 timer1 oscillator a low-power 32.768 khz crystal oscillator is built-in between pins osc1 (input) and osc2 (output). the oscillator is enabled by setting the t1oscen control bit of the t1con register. the oscillator will continue to run during sleep. the timer1 oscillator is shared with the system lp oscillator. thus, timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when the oscillator is in the lp oscillator mode. the user must provide a software time delay to ensure proper oscillator start-up. trisa5 and trisa4 bits are set when the timer1 oscillator is enabled. ra5 and ra4 bits read as ? 0 ? and trisa5 and trisa4 bits read as ? 1 ?. 6.5 timer1 operation in asynchronous counter mode if control bit t1sync of the t1con register is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 6.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 6.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmr1h:tmr1l register pair. 6.6 timer1 gate timer1 gate source is software configurable to be the t1g pin or the output of comparator c2. this allows the device to directly time external events using t1g or analog events using comparator c2. see the cm2con1 register (register 8-3) for selecting the timer1 gate source. this feature can simplify the software for a delta-sigma a/d converter and many other applications. for more information on delta-sigma a/d converters, see the microchip web site (www.microchip.com). timer1 gate can be inverted using the t1ginv bit of the t1con register, whether it originates from the t1g pin or comparator c2 output. this configures timer1 to measure either the active-high or active-low time between events. note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to enabling timer1. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. note: tmr1ge bit of the t1con register must be set to use either t1g or c2out as the timer1 gate source. see the cm2con1 register (register 8-3) for more informa- tion on selecting the timer1 gate source.
? 2007 microchip technology inc. preliminary ds41288c-page 49 pic16f610/616/16hv610/616 6.7 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: ? tmr1ie bit of the pie1 register ? peie bit of the intcon register ? gie bit of the intcon register ? t1sync bit of the t1con register ? tmr1cs bit of the t1con register ? t1oscen bit of the t1con register (can be set) the interrupt is cleared by clearing the tmr1if bit in the interrupt service routine. 6.8 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: ? tmr1on bit of the t1con register must be set ? tmr1ie bit of the pie1 register must be set ? peie bit of the intcon register must be set the device will wake-up on an overflow and execute the next instruction. if the gie bit of the intcon register is set, the device will call the interrupt service routine (0004h). 6.9 eccp capture/compare time base (PIC16F616/16hv616 only) the eccp module uses the tmr1h:tmr1l register pair as the time base when operating in capture or compare mode. in capture mode, the value in the tmr1h:tmr1l register pair is copied into the ccpr1h:ccpr1l register pair on a configured event. in compare mode, an event is triggered when the value ccpr1h:ccpr1l register pair matches the value in the tmr1h:tmr1l register pair. this event can be a special event trigger. for more information, see section 10.0 ?enhanced capture/compare/pwm (with auto-shutdown and dead band) module (PIC16F616/16hv616 only)? . 6.10 eccp special event trigger (PIC16F616/16hv616 only) when the eccp is configured to trigger a special event, the trigger will clear the tmr1h:tmr1l register pair. this special event does not cause a timer1 inter- rupt. the eccp module may still be configured to gen- erate a eccp interrupt. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer1. timer1 should be synchronized to the f osc to utilize the special event trigger. asynchronous operation of timer1 can cause a special event trigger to be missed. in the event that a write to tmr1h or tmr1l coincides with a special event trigger from the eccp, the write will take precedence. for more information, see section 10.2.4 ?special event trigger? . 6.11 comparator synchronization the same clock used to increment timer1 can also be used to synchronize the comparator output. this feature is enabled in the comparator module. when using the comparator for timer1 gate, the comparator output should be synchronized to timer1. this ensures timer1 does not miss an increment if the comparator changes. for more information, see section 8.8.2 ?synchronizing comparator c2 output to timer1? . figure 6-2: timer1 incrementing edge note: the tmr1h:ttmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the count er prior to the first incrementing rising edge of the clock .
pic16f610/616/16hv610/616 ds41288c-page 50 preliminary ? 2007 microchip technology inc. 6.12 timer1 control register the timer1 control register (t1con), shown in register 6-1, is used to control timer1 and select the various features of the timer1 module. register 6-1: t1con: timer1 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ginv (1) tmr1ge (2) t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 t1ginv: timer1 gate invert bit (1) 1 = timer1 gate is active-high (timer1 counts when gate is high) 0 = timer1 gate is active-low (timer1 counts when gate is low) bit 6 tmr1ge: timer1 gate enable bit (2) if tmr1on = 0 : this bit is ignored if tmr1on = 1 : 1 = timer1 counting is controlled by the timer1 gate function 0 = timer1 is always counting bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit if intosc without clkout oscillator is active: 1 = lp oscillator is enabled for timer1 clock 0 = lp oscillator is off else: this bit is ignored bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from t1cki pin (on the rising edge) 0 = internal clock if tmr1acs = 0 : fosc/4 if tmr1acs = 1 : fosc bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 note 1: t1ginv bit inverts the timer1 gate logic, regardless of source. 2: tmr1ge bit must be set to use either t1g pin or c2out, as selected by the t1gss bit of the cm2con1 register, as a timer1 gate source.
? 2007 microchip technology inc. preliminary ds41288c-page 51 pic16f610/616/16hv610/616 table 6-1: summary of registers associated with timer1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets cm2con0 c2on c2out c2oe c2pol ? c2r c2ch1 c2ch0 0000 -000 0000 -000 cm2con1 mc1out mc2out ?t1acs c1hys c2hys t1gss c2sync 00-0 0010 00-0 0010 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 ? adie (1) ccp1ie (1) c2ie c1ie ? tmr2ie (1) tmr1ie -000 0-00 -000 0-00 pir1 ? adif (1) ccp1if (1) c2if c1if ? tmr2if (1) tmr1if -000 0-00 -000 0-00 tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. note 1: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 52 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 53 pic16f610/616/16hv610/616 7.0 timer2 module (PIC16F616/16hv616 only) the timer2 module is an 8-bit timer with the following features: ? 8-bit timer register (tmr2) ? 8-bit period register (pr2) ? interrupt on tmr2 match with pr2 ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) see figure 7-1 for a block diagram of timer2. 7.1 timer2 operation the clock input to the timer2 module is the system instruction clock (f osc /4). the clock is fed into the timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. the output of the prescaler is then used to increment the tmr2 register. the values of tmr2 and pr2 are constantly compared to determine when they match. tmr2 will increment from 00h until it matches the value in pr2. when a match occurs, two things happen: ? tmr2 is reset to 00h on the next increment cycle. ? the timer2 postscaler is incremented the match output of the timer2/pr2 comparator is then fed into the timer2 postscaler. the postscaler has postscale options of 1:1 to 1:16 inclusive. the output of the timer2 postscaler is used to set the tmr2if interrupt flag bit in the pir1 register. the tmr2 and pr2 registers are both fully readable and writable. on any reset, the tmr2 register is set to 00h and the pr2 register is set to ffh. timer2 is turned on by setting the tmr2on bit in the t2con register to a ? 1 ?. timer2 is turned off by setting the tmr2on bit to a ? 0 ?. the timer2 prescaler is controlled by the t2ckps bits in the t2con register. the timer2 postscaler is controlled by the toutps bits in the t2con register. the prescaler and postscaler counters are cleared when: ? a write to tmr2 occurs. ? a write to t2con occurs. ? any device reset occurs (power-on reset, mclr reset, watchdog timer reset, or brown-out reset). figure 7-1: timer2 block diagram note: tmr2 is not cleared when t2con is written. comparator tmr2 sets flag tmr2 output reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if toutps<3:0> t2ckps<1:0>
pic16f610/616/16hv610/616 ds41288c-page 54 preliminary ? 2007 microchip technology inc. table 7-1: summary of associated timer2 registers register 7-1: t2con: timer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps<3:0>: timer2 output postscaler select bits 0000 = 1:1 postscaler 0001 = 1:2 postscaler 0010 = 1:3 postscaler 0011 = 1:4 postscaler 0100 = 1:5 postscaler 0101 = 1:6 postscaler 0110 = 1:7 postscaler 0111 = 1:8 postscaler 1000 = 1:9 postscaler 1001 = 1:10 postscaler 1010 = 1:11 postscaler 1011 = 1:12 postscaler 1100 = 1:13 postscaler 1101 = 1:14 postscaler 1110 = 1:15 postscaler 1111 = 1:16 postscaler bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 ? adie (1) ccp1ie (1) c2ie c1ie ?tmr2ie (1) tmr1ie -000 0-00 -000 0-00 pir1 ? adif (1) ccp1if (1) c2if c1if ?tmr2if (1) tmr1if -000 0-00 -000 0-00 pr2 timer2 module period register 1111 1111 1111 1111 tmr2 holding register for the 8-bit tmr2 register 0000 0000 0000 0000 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?. shaded cells are not used for timer2 module. note 1: PIC16F616/16hv616 only.
? 2007 microchip technology inc. preliminary ds41288c-page 55 pic16f610/616/16hv610/616 8.0 comparator module comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. the comparators are very useful mixed signal building blocks because they provide analog functionality independent of the device. the analog comparator module includes the following features: ? independent comparator control ? programmable input selection ? comparator output is available internally/externally ? programmable output polarity ? interrupt-on-change ? wake-up from sleep ?pwm shutdown ? timer1 gate (count enable) ? output synchronization to timer1 clock input ?sr latch ? programmable and fixed voltage reference ? user-enable comparator hysteresis 8.1 comparator overview a single comparator is shown in figure 8-1 along with the relationship between the analog input levels and the digital output. when the analog voltage at v in + is less than the analog voltage at v in -, the output of the comparator is a digital low level. when the analog voltage at v in + is greater than the analog voltage at v in -, the output of the comparator is a digital high level. figure 8-1: single comparator note: only comparator c2 can be linked to timer1. ? + v in + v in - output output v in + v in - note: the black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
pic16f610/616/16hv610/616 ds41288c-page 56 preliminary ? 2007 microchip technology inc. figure 8-2: comparator c1 simplified block diagram figure 8-3: comparator c2 simplified block diagram note 1: when c1on = 0 , the c1 comparator will produce a ? 0 ? output to the xor gate. 2: output shown for reference only. see i/o port pin block diagram for more detail. c1pol c1out to pwm logic c1oe rd_cm1con0 set c1if to dq en q1 data bus c1pol dq en cl q3*rd_cm1con0 reset c1out pin (2) mux c1 0 1 2 3 c1on (1) c1ch<1:0> 2 0 1 c1r c1v ref mux c1v in - c1v in + c12in0- c12in1- c12in2- c12in3- c1in+ + - mux c2 c2pol c2out to other peripherals 0 1 2 3 c2on (1) c2ch<1:0> 2 0 1 c2r from timer1 clock note 1: when c2on = 0 , the c2 comparator will produce a ? 0 ? output to the xor gate. 2: output shown for reference only. see i/o port pin block diagram for more detail. c2oe c2v ref mux dq en dq en cl dq rd_cm2con0 q3*rd_cm2con0 q1 set c2if to reset c2v in - c2v in + c2out pin (2) c2in+ c12in0- c12in1- c2in2- c2in3- 0 1 c2sync c2pol data bus mux syncc2out to timer1 gate to sr latch
? 2007 microchip technology inc. preliminary ds41288c-page 57 pic16f610/616/16hv610/616 8.2 comparator control each comparator has a separate control and configuration register: cm1con0 for comparator c1 and cm2con0 for comparator c2. in addition, comparator c2 has a second control register, cm2con1, for controlling the interaction with timer1 and simultaneous reading of both comparator outputs. the cm1con0 and cm2con0 registers (see registers 8-1 and 8-2, respectively) contain the control and status bits for the following: ? enable ? input selection ? reference selection ?output selection ? output polarity 8.2.1 comparator enable setting the cxon bit of the cmxcon0 register enables the comparator for operation. clearing the cxon bit disables the comparator for minimum current consumption. 8.2.2 comparator input selection the cxch<1:0> bits of the cmxcon0 register direct one of four analog input pins to the comparator inverting input. 8.2.3 comparator reference selection setting the cxr bit of the cmxcon0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. see section 8.11 ?comparator voltage reference? for more information on the internal voltage reference module. 8.2.4 comparator output selection the output of the comparator can be monitored by reading either the cxout bit of the cmxcon0 register or the mcxout bit of the cm2con1 register. in order to make the output available for an external connection, the following conditions must be true: ? cxoe bit of the cmxcon0 register must be set ? corresponding tris bit must be cleared ? cxon bit of the cmxcon0 register must be set. 8.2.5 comparator output polarity inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. the polarity of the comparator output can be inverted by setting the cxpol bit of the cmxcon0 register. clearing the cxpol bit results in a non-inverted output. table 8-1 shows the output state versus input conditions, including polarity control. 8.3 comparator response time the comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. this period is referred to as the response time. the response time of the comparator differs from the settling time of the voltage reference. therefore, both of these times must be considered when determining the total response time to a comparator input change. see the comparator and voltage reference specifications in section 15.0 ?electrical specifications? for more details. note: to use cxin+ and cxin- pins as analog inputs, the appropriate bits must be set in the ansel register and the corresponding tris bits must also be set to disable the output drivers. note 1: the cxoe bit overrides the port data latch. setting the cxon has no impact on the port override. 2: the internal output of the comparator is latched with each instruction cycle. unless otherwise specified, external outputs are not latched. table 8-1: comparator output state vs. input conditions input condition cxpol cxout cxv in - > cxv in + 00 cxv in - < cxv in + 01 cxv in - > cxv in + 11 cxv in - < cxv in + 10
pic16f610/616/16hv610/616 ds41288c-page 58 preliminary ? 2007 microchip technology inc. 8.4 comparator interrupt operation the comparator interrupt flag can be set whenever there is a change in the output value of the comparator. changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see figure 8-2 and figure 8-3). one latch is updated with the comparator output level when the cmxcon0 register is read. this latch retains the value until the next read of the cmxcon0 register or the occurrence of a reset. the other latch of the mismatch circuit is updated on every q1 system clock. a mismatch condition will occur when a comparator output change is clocked through the second latch on the q1 clock cycle. at this point the two mismatch latches have opposite output levels which is detected by the exclusive-or gate and fed to the interrupt circuitry. the mismatch condition persists until either the cmxcon0 register is read or the comparator output returns to the previous state. the comparator interrupt is set by the mismatch edge and not the mismatch level. this means that the inter- rupt flag can be reset without the additional step of reading or writing the cmxcon0 register to clear the mismatch registers. when the mismatch registers are cleared, an interrupt will occur upon the comparator?s return to the previous state, otherwise no interrupt will be generated. software will need to maintain information about the status of the comparator output, as read from the cmxcon0 register, or cm2con1 register, to determine the actual change that has occurred. the cxif bit of the pir1 register is the comparator interrupt flag. this bit must be reset in software by clearing it to ? 0 ?. since it is also possible to write a ? 1 ? to this register, an interrupt can be generated. the cxie bit of the pie1 register and the peie and gie bits of the intcon register must all be set to enable comparator interrupts. if any of these bits are cleared, the interrupt is not enabled, although the cxif bit of the pir1 register will still be set if an interrupt condition occurs. figure 8-4: comparator interrupt timing w/o cmxcon0 read figure 8-5: comparator interrupt timing with cmxcon0 read note 1: a write operation to the cmxcon0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. 2: comparator interrupts will operate correctly regardless of the state of cxoe. note 1: if a change in the cmxcon0 register (cxout) should occur when a read oper- ation is being executed (start of the q2 cycle), then the cxif of the pir1 register interrupt flag may not get set. 2: when either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. q1 q3 cxin+ cxout set cxif (edge) cxif t rt reset by software q1 q3 cxin+ cxout set cxif (edge) cxif t rt reset by software cleared by cmxcon0 read
? 2007 microchip technology inc. preliminary ds41288c-page 59 pic16f610/616/16hv610/616 8.5 operation during sleep the comparator, if enabled before entering sleep mode, remains active during sleep. the additional current consumed by the comparator is shown separately in section 15.0 ?electrical specifications? . if the comparator is not used to wake the device, power consumption can be minimized while in sleep mode by turning off the comparator. each comparator is turned off by clearing the cxon bit of the cmxcon0 register. a change to the comparator output can wake-up the device from sleep. to enable the comparator to wake the device from sleep, the cxie bit of the pie1 register and the peie bit of the intcon register must be set. the instruction following the sleep instruction always executes following a wake from sleep. if the gie bit of the intcon register is also set, the device will then execute the interrupt service routine. 8.6 effects of a reset a device reset forces the cmxcon0 and cm2con1 registers to their reset states. this forces both comparators and the voltage references to their off states.
pic16f610/616/16hv610/616 ds41288c-page 60 preliminary ? 2007 microchip technology inc. register 8-1: cm1con0: compa rator 1 control register 0 r/w-0 r-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 c1on c1out c1oe c1pol ? c1r c1ch1 c1ch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1on: comparator c1 enable bit 1 = comparator c1 is enabled 0 = comparator c1 is disabled bit 6 c1out: comparator c1 output bit if c1pol = 1 (inverted polarity): c1out = 0 when c1v in + > c1v in - c1out = 1 when c1v in + < c1v in - if c1pol = 0 (non-inverted polarity): c1out = 1 when c1v in + > c1v in - c1out = 0 when c1v in + < c1v in - bit 5 c1oe: comparator c1 output enable bit 1 = c1out is present on the c1out pin (1) 0 = c1out is internal only bit 4 c1pol: comparator c1 output polarity select bit 1 = c1out logic is inverted 0 = c1out logic is not inverted bit 3 unimplemented: read as ? 0 ? bit 2 c1r: comparator c1 reference select bit (non-inverting input) 1 = c1v in + connects to c1v ref output 0 = c1v in + connects to c1in+ pin bit 1-0 c1ch<1:0>: comparator c1 channel select bit 00 = c12in0- pin of c1 connects to c1v in - 01 = c12in1- pin of c1 connects to c1v in - 10 = c12in2- pin of c1 connects to c1v in - 11 = c12in3- pin of c1 connects to c1v in - note 1: comparator output requires the following three conditions: c1oe = 1 , c1on = 1 and corresponding port tris bit = 0 .
? 2007 microchip technology inc. preliminary ds41288c-page 61 pic16f610/616/16hv610/616 register 8-2: cm2con0: compa rator 2 control register 0 r/w-0 r-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 c2on c2out c2oe c2pol ? c2r c2ch1 c2ch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c2on: comparator c2 enable bit 1 = comparator c2 is enabled 0 = comparator c2 is disabled bit 6 c2out: comparator c2 output bit if c2pol = 1 (inverted polarity): c2out = 0 when c2v in + > c2v in - c2out = 1 when c2v in + < c2v in - if c2pol = 0 (non-inverted polarity): c2out = 1 when c2v in + > c2v in - c2out = 0 when c2v in + < c2v in - bit 5 c2oe: comparator c2 output enable bit 1 = c2out is present on c2out pin (1) 0 = c2out is internal only bit 4 c2pol: comparator c2 output polarity select bit 1 = c2out logic is inverted 0 = c2out logic is not inverted bit 3 unimplemented: read as ? 0 ? bit 2 c2r: comparator c2 reference select bits (non-inverting input) 1 = c2v in + connects to c2v ref 0 = c2v in + connects to c2in+ pin bit 1-0 c2ch<1:0>: comparator c2 channel select bits 00 = c2v in - pin of c2 connects to c12in0- 01 = c2v in - pin of c2 connects to c12in1- 10 = c2v in - pin of c2 connects to c12in2- 11 = c2v in - pin of c2 connects to c12in3- note 1: comparator output requires the following three conditions: c2oe = 1 , c2on = 1 and corresponding port tris bit = 0 .
pic16f610/616/16hv610/616 ds41288c-page 62 preliminary ? 2007 microchip technology inc. 8.7 comparator analog input connection considerations a simplified circuit for an analog input is shown in figure 8-6. since the analog input pins share their con- nection with a digital input, they have reverse biased esd protection diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k is recommended for the analog sources. also, any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current to minimize inaccuracies introduced. figure 8-6: analog input model note 1: when reading a port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert as an analog input, according to the input specification. 2: analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. v a rs < 10k c pin 5 pf v dd v t 0.6v v t 0.6v r ic i leakage 500 na vss a in legend: c pin = input capacitance i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance v a = analog voltage v t = threshold voltage to adc input
? 2007 microchip technology inc. preliminary ds41288c-page 63 pic16f610/616/16hv610/616 8.8 additional comparator features there are three additional comparator features: ? timer1 count enable (gate) ? synchronizing output with timer1 ? simultaneous read of comparator outputs 8.8.1 comparator c2 gating timer1 this feature can be used to time the duration or interval of analog events. clearing the t1gss bit of the cm2con1 register will enable timer1 to increment based on the output of comparator c2. this requires that timer1 is on and gating is enabled. see section 6.0 ?timer1 module with gate control? for details. it is recommended to synchronize the comparator with timer1 by setting the c2sync bit when the comparator is used as the timer1 gate source. this ensures timer1 does not miss an increment if the comparator changes during an increment. 8.8.2 synchronizing comparator c2 output to timer1 the comparator c2 output can be synchronized with timer1 by setting the c2sync bit of the cm2con1 register. when enabled, the c2 output is latched on the falling edge of the timer1 clock source. if a prescaler is used with timer1, the comparator output is latched after the prescaling function. to prevent a race condition, the comparator output is latched on the falling edge of the timer1 clock source and timer1 increments on the rising edge of its clock source. see the comparator block diagram (figure 8-3) and the timer1 block diagram (figure 6-1) for more information. 8.8.3 simultaneous comparator output read the mc1out and mc2out bits of the cm2con1 register are mirror copies of both comparator outputs. the ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. note 1: obtaining the status of c1out or c2out by reading cm2con1 does not affect the comparator interrupt mismatch registers. register 8-3: cm2con1: compa rator 2 control register 1 r-0 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-0 mc1out mc2out ? t1acs c1hys c2hys t1gss c2sync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 mc1out: mirror copy of c1out bit bit 6 mc2out: mirror copy of c2out bit bit 5 unimplemented: read as ? 0 ? bit 4 t1acs: timer1 alternate clock select bit 1 = timer1 clock source is the system clock (f osc ) 0 = timer1 clock source is the internal clock f osc /4) bit 3 c1hys: comparator c1 hysteresis enable bit 1 = comparator c1 hysteresis enabled 0 = comparator c1 hysteresis disabled bit 2 c2hys: comparator c2 hysteresis enable bit 1 = comparator c2 hysteresis enabled 0 = comparator c2 hysteresis disabled bit 1 t1gss: timer1 gate source select bit 1 = timer1 gate source is t1g 0 = timer1 gate source is syncc2out. bit 0 c2sync: comparator c2 output synchronization bit 1 = c2 output is synchronous to falling edge of timer1 clock 0 = c2 output is asynchronous
pic16f610/616/16hv610/616 ds41288c-page 64 preliminary ? 2007 microchip technology inc. 8.9 comparator hysteresis each comparator has built-in hysteresis that is user enabled by setting the c1hys or c2hys bits of the cm2con1 register. the hysteresis feature can help filter noise and reduce multiple comparator output transitions when the output is changing state. figure 8-9 shows the relationship between the analog input levels and digital output of a comparator with and without hysteresis. the output of the comparator changes from a low state to a high state only when the analog voltage at v in + rises above the upper hysteresis threshold (v h +). the output of the comparator changes from a high state to a low state only when the analog voltage at v in + falls below the lower hysteresis threshold (v h -). figure 8-7: comparator hysteresis ? + v in + v in - output note: the black areas of the comparator output represents the uncertainty due to input offsets and response time . v h - v h + v in - v+ v in + output (without hysteresis) output (with hysteresis)
? 2007 microchip technology inc. preliminary ds41288c-page 65 pic16f610/616/16hv610/616 table 8-2: summary of registers associated with the comparator and voltage reference modules name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 0000 0000 cm2con1 mc1out mc2out ? t1acs c1hys c2hys t1gss c2sync 00-0 0010 00-0 0010 intcon gie peie t0ie inte raie t0if intf raif 0000 000x 0000 000x pie1 ? adie (1) ccp1ie (1) c2ie c1ie ? tmr2ie (1) tmr1ie -000 0-00 -000 0-00 pir1 ? adif (1) ccp1if (1) c2if c1if ? tmr2if (1) tmr1if -000 0-00 -000 0-00 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 --x0 x000 portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx 00xx --uu 00uu srcon0 sr1 sr0 c1sen c2ren pulss pulsr ? srclken 0000 00-0 0000 00-0 srcon1 srcs1 srcs0 ? ? ? ? ? ? 00-- ---- 00-- ---- trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 trisc trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 vrcon c1vren c2vren vrr fvren vr3 vr2 vr1 vr0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used for comparator. note 1: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 66 preliminary ? 2007 microchip technology inc. 8.10 comparator sr latch the sr latch module provides additional control of the comparator outputs. the module consists of a single sr latch and output multiplexers. the sr latch can be set, reset or toggled by the comparator outputs. the sr latch may also be set or reset, independent of comparator output, by control bits in the srcon0 control register. the sr latch output multiplexers select whether the latch outputs or the comparator outputs are directed to the i/o port logic for eventual output to a pin. the sr latch also has a variable clock, which is con- nected to the set input of the latch. the srclken bit of srcon0 enables the sr latch set clock. the clock will periodically pulse the set input of the latch. control over the frequency of the sr latch set clock is provided by the srcs<1:0> bits of srcon1 register. 8.10.1 latch operation the latch is a set-reset latch that does not depend on a clock source. each of the set and reset inputs are active-high. each latch input is connected to a comparator output and a software controlled pulse generator. the latch can be set by c1out or the pulss bit of the srcon0 register. the latch can be reset by c2out or the pulsr bit of the srcon0 register. the latch is reset-dominant, therefore, if both set and reset inputs are high the latch will go to the reset state. both the pulss and pulsr bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch set or reset operation. 8.10.2 latch output the sr<1:0> bits of the srcon0 register control the latch output multiplexers and determine four possible output configurations. in these four configurations, the cxout i/o port logic is connected to: ? c1out and c2out ? c1out and sr latch q ? c2out and sr latch q ? sr latch q and q after any reset, the default output configuration is the unlatched c1out and c2out mode. this maintains compatibility with devices that do not have the sr latch feature. the applicable tris bits of the corresponding ports must be cleared to enable the port pin output drivers. additionally, the cxoe comp arator output enable bits of the cmxcon0 registers must be set in order to make the comparator or latch outputs available on the output pins. the latch configuration enable states are completely independent of the enable states for the comparators. figure 8-8: sr latch simplified block diagram c1sen sr0 pulss s r q q c2ren pulsr sr1 note 1: if r = 1 and s = 1 simultaneously, q = 0 , q = 1 2: pulse generator causes a 1 t osc pulse width. 3: output shown for reference only. see i /o port pin block diagram for more detail. pulse gen ( 2 ) pulse gen ( 2 ) syncc2out (from comparator) c1out (from comparator) c2oe c2out pin (3) c1oe c1out pin (3) 0 1 mux 1 0 mux sr latch (1) srclken srclk
? 2007 microchip technology inc. preliminary ds41288c-page 67 pic16f610/616/16hv610/616 register 8-4: srcon0: sr latch control 0 register r/w-0 r/w-0 r/w-0 r/w-0 r/s-0 r/s-0 u-0 r/w-0 sr1 (2) sr0 (2) c1sen c2ren pulss pulsr ? srclken bit 7 bit 0 legend: s = bit is set only - r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 sr1: sr latch configuration bit (2) 1 = c2out pin is the latch q output 0 = c2out pin is the c2 comparator output bit 6 sr0: sr latch configuration bits (2) 1 = c1out pin is the latch q output 0 = c1out pin is the c1 comparator output bit 5 c1sen: c1 set enable bit 1 = c1 comparator output sets sr latch 0 = c1 comparator output has no effect on sr latch bit 4 c2ren: c2 reset enable bit 1 = c2 comparator output resets sr latch 0 = c2 comparator output has no effect on sr latch bit 3 pulss: pulse the set input of the sr latch bit 1 = triggers pulse generator to set sr latch. bit is immediately reset by hardware. 0 = does not trigger pulse generator bit 2 pulsr: pulse the reset input of the sr latch bit 1 = triggers pulse generator to reset sr latch. bit is immediately reset by hardware. 0 = does not trigger pulse generator bit 1 unimplemented: read as ? 0 ? bit 0 srclken: sr latch set clock enable bit 1 = set input of sr latch is pulsed with srclk 0 = set input of sr latch is not pulsed with the srclk note 1: the c1out and c2out bits in the cmxcon0 register will always reflect the actual comparator output (not the level on the pin), regardless of the sr latch operation. 2: to enable an sr latch output to the pin, the appropria te cxoe, and tris bits mu st be properly configured. register 8-5: srcon1: sr latch control 1 register r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 srcs1 srcs0 ? ? ? ? ? ? bit 7 bit 0 legend: s = bit is set only - r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 srcs<1:0>: sr latch clock prescale bits 00 = f osc /16 01 = f osc /32 10 = f osc /64 11 = f osc /128 bit 5-0 unimplemented: read as ? 0 ?
pic16f610/616/16hv610/616 ds41288c-page 68 preliminary ? 2007 microchip technology inc. 8.11 comparator voltage reference the comparator voltage reference module provides an internally generated voltage reference for the compara- tors. the following features are available: ? independent from comparator operation ? two 16-level voltage ranges ? output clamped to v ss ? ratiometric with v dd ? fixed reference (0.6v) the vrcon register (register 8-6) controls the voltage reference module shown in figure 8-9. 8.11.1 independent operation the comparator voltage reference is independent of the comparator configuration. setting the fvren bit of the vrcon register will enable the voltage reference. 8.11.2 output voltage selection the cv ref voltage reference has 2 ranges with 16 voltage levels in each range. range selection is controlled by the vrr bit of the vrcon register. the 16 levels are set with the vr<3:0> bits of the vrcon register. the cv ref output voltage is determined by the following equations: equation 8-1: cv ref output voltage the full range of v ss to v dd cannot be realized due to the construction of the module. see figure 8-9. 8.11.3 output clamped to v ss the fixed voltage reference output voltage can be set to vss with no power consumption by clearing the fvren bit of the vrcon register (fvren = 0 ). this allows the comparator to detect a zero-crossing while not consuming additional module current. 8.11.4 output ratiometric to vdd the comparator voltage reference is v dd derived and therefore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the comparator voltage reference can be found in section 15.0 ?electrical specifications? . v rr 1 (low range): = v rr 0 (high range): = cv ref (v dd /4) + = cv ref (vr<3:0>/24) v dd = (vr<3:0> v dd /32)
? 2007 microchip technology inc. preliminary ds41288c-page 69 pic16f610/616/16hv610/616 8.11.5 fixed voltage reference the fixed voltage reference is independent of v dd , with a nominal output voltage of 0.6v. this reference can be enabled by setting the fvren bit of the vrcon register to ? 1 ?. this reference is always enabled when the hfintosc oscillator is active. 8.11.6 fixed voltage reference stabilization period when the fixed voltage reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. the user program must include a small delay routine to allow the module to settle. see the electrical specifications section for the minimum delay requirement. 8.11.7 voltage reference selection multiplexers on the output of the voltage reference module enable selection of either the cv ref or fixed voltage reference for use by the comparators. setting the c1vren bit of the vrcon register enables current to flow in the cv ref voltage divider and selects the cv ref voltage for use by c1. clearing the c1vren bit selects the fixed voltage for use by c1. setting the c2vren bit of the vrcon register enables current to flow in the cv ref voltage divider and selects the cv ref voltage for use by c2. clearing the c2vren bit selects the fixed voltage for use by c2. when both the c1vren and c2vren bits are cleared, current flow in the cv ref voltage divider is disabled minimizing the power drain of the voltage reference peripheral. figure 8-9: comparator voltage reference block diagram v rr 8r vr<3:0> (1) analog 8rrr rr 16 stages v dd mux fixed voltage c2vren c1vren cv ref reference en fvren 0.6v fixed ref to comparators and adc module to comparators and adc module note 1: care should be taken to ensure v ref remains within the comparator common mode input range. see section 15.0 ?electrical specifications? for more detail. 4 15 0 1.2v to adc module
pic16f610/616/16hv610/616 ds41288c-page 70 preliminary ? 2007 microchip technology inc. register 8-6: vrcon: voltage reference control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c1vren c2vren vrr fvren vr3 vr2 vr1 vr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1vren: comparator 1 voltage reference enable bit 1 = cv ref circuit powered on and routed to c1v ref input of comparator c1 0 = 0.6 volt constant reference routed to c1v ref input of comparator c1 bit 6 c2vren: comparator 2 voltage reference enable bit 1 = cv ref circuit powered on and routed to c2v ref input of comparator c2 0 = 0.6 volt constant reference routed to c2v ref input of comparator c2 bit 5 vrr: cv ref range selection bit 1 = low range 0 = high range bit 4 fvren: fixed voltage reference (0.6v) enable bit 1 = enabled 0 = disabled bit 3-0 vr<3:0>: comparator voltage reference cv ref value selection bits (0 vr<3:0> 15) when v rr = 1 : cv ref = (vr<3:0>/24) * v dd when v rr = 0 : cv ref = v dd /4 + (vr<3:0>/32) * v dd
? 2007 microchip technology inc. preliminary ds41288c-page 71 pic16f610/616/16hv610/616 9.0 analog-to-digital converter (adc) module (PIC16F616/16hv616 only) the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresl and adresh). the adc voltage reference is software selectable to either v dd or a voltage applied to the external reference pins. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 9-1 shows the block diagram of the adc. figure 9-1: adc block diagram adc v dd v ref adon go/done vcfg = 1 vcfg = 0 chs <3:0> v ss ra0/an0 ra1/an1/v ref ra2/an2 ra4/an3 rc0/an4 rc1/an5 rc2/an6 rc3/an7 cv ref 0.6v reference 1.2v reference adresh adresl 10 10 adfm 0 = left justify 1 = right justify 4
pic16f610/616/16hv610/616 ds41288c-page 72 preliminary ? 2007 microchip technology inc. 9.1 adc configuration when configuring and using the adc, the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? results formatting 9.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. see the corresponding port section for more information. 9.1.2 channel selection the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 9.2 ?adc operation? for more information. 9.1.3 adc v oltage reference the vcfg bit of the adcon0 register provides control of the positive voltage reference. the positive voltage reference can be either v dd or an external voltage source. the negative voltage reference is always connected to the ground reference. 9.1.4 conversion clock the source of the conversion clock is software select- able via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11 t ad periods as shown in figure 9-3. for correct conversion, the appropriate t ad specification must be met. see a/d conversion requirements in section 15.0 ?electrical specifications? for more information. table 9-1 gives examples of appropriate adc clock selections. table 9-1: adc clock period (t ad ) v s . device operating frequencies (v dd > 3.0v) note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result. adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 20 mhz 8 mhz 4 mhz 1 mhz f osc /2 000 100 ns (2) 250 ns (2) 500 ns (2) 2.0 s f osc /4 100 200 ns (2) 500 ns (2) 1.0 s (2) 4.0 s f osc /8 001 400 ns (2) 1.0 s (2) 2.0 s 8.0 s (3) f osc /16 101 800 ns (2) 2.0 s4.0 s 16.0 s (3) f osc /32 010 1.6 s4.0 s 8.0 s (3) 32.0 s (3) f osc /64 110 3.2 s 8.0 s (3) 16.0 s (3) 64.0 s (3) f rc x11 2-6 s (1,4) 2-6 s (1,4) 2-6 s (1,4) 2-6 s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 4 s for v dd > 3.0v. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the f rc clock source is only recommended if the conversion will be performed during sleep.
? 2007 microchip technology inc. preliminary ds41288c-page 73 pic16f610/616/16hv610/616 figure 9-2: analog-to-digital conversion t ad cycles 9.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruction is always executed. if the user is attempting to wake-up from sleep and resume in-line code execution, the global interrupt must be disabled. if the global interrupt is enabled, execution will switch to the interrupt service routine. please see section 9.1.5 ?interrupts? for more information. 9.1.6 result formatting the 10-bit a/d conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon0 register controls the output format. figure 9-4 shows the two output formats. figure 9-3: 10-bit a/d conversion result format t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 10 t ad 11 b1 b0 t cy to t ad conversion starts adresh and adresl registers are loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input note: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. adresh adresl (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit a/d result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit a/d result
pic16f610/616/16hv610/616 ds41288c-page 74 preliminary ? 2007 microchip technology inc. 9.2 adc operation 9.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/ done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 9.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif flag bit ? update the adresh:adresl registers with new conversion result 9.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh:adresl registers will not be updated with the partially complete analog-to-digital conversion sample. instead, the adresh:adresl register pair will retain the value of the previous conversion. addi- tionally, a 2 t ad delay is required before another acqui- sition can be initiated. following this delay, an input acquisition is automatically started on the selected channel. 9.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc clock source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conver- sion to be aborted and the adc module is turned off, although the adon bit remains set. 9.2.5 special event trigger the eccp special event trigger allows periodic adc measurements without software intervention. when this trigger occurs, the go/done bit is set by hardware and the timer1 counter resets to zero. using the special event trigger does not ensure proper adc timing. it is the user?s responsibility to ensure that the adc timing requirements are met. see section 10.0 ?enhanced capture/compare/ pwm (with auto-shutdown and dead band) mod- ule (PIC16F616/16hv616 only)? for more informa- tion. 9.2.6 a/d conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (see tris register) ? configure pin as analog 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? select result format ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result 8. clear the adc interrupt flag (required if interrupt is enabled). note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 9.2.6 ?a/d conversion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. note 1: the global interrupt may be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: see section 9.3 ?a/d acquisition requirements? .
? 2007 microchip technology inc. preliminary ds41288c-page 75 pic16f610/616/16hv610/616 example 9-1: a/d conversion ;this code block configures the adc ;for polling, vdd reference, frc clock ;and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?01110000? ;adc frc clock movwf adcon1 ; banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel adcon0 ; movlw b?10000001? ;right justify, movwf adcon0 ;vdd vref, an0, on call sampletime ;acquisiton delay bsf adcon0,go ;start conversion btfsc adcon0,go ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adresl ; movf adresl,w ;read lower 8 bits movwf resultlo ;store in gpr space
pic16f610/616/16hv610/616 ds41288c-page 76 preliminary ? 2007 microchip technology inc. 9.2.7 adc register definitions the following registers are used to control the operation of the adc. register 9-1: adcon0: a/d control register 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm vcfg chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d conversion result format select bit 1 = right justified 0 = left justified bit 6 vcfg: voltage reference bit 1 = v ref pin 0 = v dd bit 5-2 chs<3:0>: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) 0110 = channel 06 (an6) 0111 = channel 07 (an7) 1000 = reserved ? do not use 1001 = reserved ? do not use 1010 = reserved ? do not use 1011 = reserved ? do not use 1100 =cv ref 1101 = 0.6v fixed voltage reference (1) 1110 = 1.2v fixed voltage reference (1) 1111 = reserved ? do not use bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setti ng this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: when the chs<3:0> bits change to select the 1.2v or 0.6v fixed voltage reference, the reference output voltage will have a transient. if the comparator module uses this vp6 reference voltage, the comparator output may momentarily change state due to the transient.
? 2007 microchip technology inc. preliminary ds41288c-page 77 pic16f610/616/16hv610/616 register 9-2: adcon1: a/d control register 1 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? adcs2 adcs1 adcs0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 adcs<2:0>: a/d conversion clock select bits 000 = f osc /2 001 = f osc /8 010 = f osc /32 x11 = f rc (clock derived from a dedicated internal oscillator = 500 khz max) 100 = f osc /4 101 = f osc /16 110 = f osc /64 bit 3-0 unimplemented: read as ? 0 ?
pic16f610/616/16hv610/616 ds41288c-page 78 preliminary ? 2007 microchip technology inc. register 9-3: adresh: adc result register high (adresh) adfm = 0 (read-only) r-x r-x r-x r-x r-x r-x r-x r-x adres9 adres8 adres7 adres6 adres5 adres4 adres3 adres2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<9:2> : adc result register bits upper 8 bits of 10-bit conversion result register 9-4: adresl: adc result register low (adresl) adfm = 0 (read-only) r-x r-x u-0 u-0 u-0 u-0 u-0 u-0 adres1 adres0 ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 adres<1:0> : adc result register bits lower 2 bits of 10-bit conversion result bit 5-0 reserved : do not use. register 9-5: adresh: adc result register high (adresh) adfm = 1 (read-only) u-0 u-0 u-0 u-0 u-0 u-0 r-x r-x ? ? ? ? ? ? adres9 adres8 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper 2 bits of 10-bit conversion result register 9-6: adresl: adc result register low (adresl) adfm = 1 (read-only) r-x r-x r-x r-x r-x r-x r-x r-x adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<7:0> : adc result register bits lower 8 bits of 10-bit conversion result
? 2007 microchip technology inc. preliminary ds41288c-page 79 pic16f610/616/16hv610/616 9.3 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 9-4. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 9-4. the maximum recommended impedance for analog sources is 10 k . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 9-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 9-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 5s t c temperature - 25c () 0.05s/c () [] ++ = t c c hold r ic r ss r s ++ () ln(1/2047) ? = 10pf 1k 7k 10k ++ () ? ln(0.0004885) = 1.37 = s t acq 5 s 1.37 s 50c- 25c () 0.05 s /c () [] ++ = 7.67 s = v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2047 ----------- - ? ?? ?? = v applied 1 1 2047 ----------- - ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k 5.0v v dd = assumptions: note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k . this is required to meet the pin leakage specification.
pic16f610/616/16hv610/616 ds41288c-page 80 preliminary ? 2007 microchip technology inc. figure 9-4: analog input model figure 9-5: adc transfer function c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss rss c hold = 10 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ) v dd 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss 3ffh 3feh adc output code 3fdh 3fch 004h 003h 002h 001h 000h full-scale 3fbh 1 lsb ideal v ss /v ref - zero-scale transition v dd /v ref + transition 1 lsb ideal full-scale range analog input voltage
? 2007 microchip technology inc. preliminary ds41288c-page 81 pic16f610/616/16hv610/616 table 9-2: summary of associated adc registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets adcon0 (1) adfm vcfg chs3 chs2 chs1 chs0 go/done adon 0000 0000 0000 0000 adcon1 (1) ? adcs2 adcs1 adcs0 ? ? ? ? -000 ---- -000 ---- ansel ans ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 adresh a/d result register high byte xxxx xxxx uuuu uuuu adresl a/d result register low byte xxxx xxxx uuuu uuuu intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 ?adie (1) ccp1ie (1) c2ie c1ie ? tmr2ie (1) tmr1ie -000 0-00 -000 0-00 pir1 ?adif (1) ccp1if (1) c2if c1if ? tmr2if (1) tmr1if -000 0-00 -000 0-00 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 --u0 u000 portc ? ? rc5 rc4 rc3 rc2 rc1 rc0 --xx 00xx --uu 00uu trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 trisc ? ? trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?. shaded cells are not used for adc module. note 1: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 82 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 83 pic16f610/616/16hv610/616 10.0 enhanced capture/ compare/pwm (with auto- shutdown and dead band) module (PIC16F616/16hv616 only) the enhanced capture/compare/pwm module is a peripheral which allows the user to time and control different events. in capture mode, the peripheral allows the timing of the duration of an event. the compare mode allows the user to trigger an external event when a predetermined amount of time has expired. the pwm mode can generate a pulse-width modulated signal of varying frequency and duty cycle. table 10-1 shows the timer resources required by the eccp module. table 10-1: eccp mode ? timer resources required eccp mode timer resource capture timer1 compare timer1 pwm timer2 register 10-1: ccp1con: enhanced ccp1 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 p1m<1:0>: pwm output configuration bits i f ccp1m<3:2> = 00 , 01 , 10 : xx = p1a assigned as capture/compare input; p1b, p1c, p1d assigned as port pins if ccp1m<3:2> = 11 : 00 = single output; p1a modulated; p1b, p1c, p1d assigned as port pins 01 = full-bridge output forward; p1d modulated; p1a active; p1b, p1c inactive 10 = half-bridge output; p1a, p1b modulated with dead-time control; p1c, p1d assigned as port pins 11 = full-bridge output reverse; p1b modulated; p1c active; p1a, p1d inactive bit 5-4 dc1b<1:0>: pwm duty cycle least significant bits capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0 ccp1m<3:0>: eccp mode select bits 0000 = capture/compare/pwm off (resets eccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (ccp1if bit is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp1 pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set; ccp1 resets tmr1 and starts an a/d conversion, if the adc module is enabled) 1100 = pwm mode; p1a, p1c active-high; p1b, p1d active-high 1101 = pwm mode; p1a, p1c active-high; p1b, p1d active-low 1110 = pwm mode; p1a, p1c active-low; p1b, p1d active-high 1111 = pwm mode; p1a, p1c active-low; p1b, p1d active-low
pic16f610/616/16hv610/616 ds41288c-page 84 preliminary ? 2007 microchip technology inc. 10.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin ccp1. an event is defined as one of the following and is configured by the ccp1m<3:0> bits of the ccp1con register: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge when a capture is made, the interrupt request flag bit ccp1if of the pir1 register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in the ccpr1h, ccpr1l register pair is read, the old captured value is overwritten by the new captured value (see figure 10-1). 10.1.1 ccp1 pin configuration in capture mode, the ccp1 pin should be configured as an input by setting the associated tris control bit. figure 10-1: capture mode operation block diagram 10.1.2 timer1 mode selection timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 10.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccp1ie interrupt enable bit of the pie1 register clear to avoid false interrupts. additionally, the user should clear the ccp1if interrupt flag bit of the pir1 register following any change in operating mode. 10.1.4 ccp prescaler there are four prescaler settings specified by the ccp1m<3:0> bits of the ccp1con register. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. to avoid this unexpected operation, turn the module off by clearing the ccp1con register before changing the prescaler (see example 10-1). example 10-1: changing between capture prescalers note: if the ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr 1 h ccpr 1 l tmr1h tmr1l set flag bit ccp1if (pir1 register) capture enable ccp1con<3:0> prescaler 1, 4, 16 and edge detect pin ccp1 system clock (f osc ) banksel ccp1con ;set bank bits to point ;to ccp1con clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; move value and ccp on movwf ccp1con ;load ccp1con with this ; value
? 2007 microchip technology inc. preliminary ds41288c-page 85 pic16f610/616/16hv610/616 table 10-2: summary of registers associated with capture name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on por, bor value on all other resets ccp1con (1) p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 ccpr1l (1) capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h (1) capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 ? adie (1) ccp1ie (1) c2ie c1ie ? tmr2ie (1) tmr1ie -000 0-00 0000 0-00 pir1 ? adif (1) ccp1if (1) c2if c1if ? tmr2if (1) tmr1if -000 0-00 0000 0-00 t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 trisc ? ?trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the capture, compare and pwm. note 1: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 86 preliminary ? 2007 microchip technology inc. 10.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the ccp1 module may: ? toggle the ccp1 output ? set the ccp1 output ? clear the ccp1 output ? generate a special event trigger ? generate a software interrupt the action on the pin is based on the value of the ccp1m<3:0> control bits of the ccp1con register. all compare modes can generate an interrupt. figure 10-2: compare mode operation block diagram 10.2.1 ccp1 pin configuration the user must configure the ccp1 pin as an output by clearing the associated tris bit. 10.2.2 timer1 mode selection in compare mode, timer1 must be running in either timer mode or synchronized counter mode. the compare operation may not work in asynchronous counter mode. 10.2.3 software interrupt mode when generate software interrupt mode is chosen (ccp1m<3:0> = 1010 ), the ccp1 module does not assert control of the ccp1 pin (see the ccp1con register). 10.2.4 special event trigger when special event trigger mode is chosen (ccp1m<3:0> = 1011 ), the ccp1 module does the following: ? resets timer1 ? starts an adc conversion if adc is enabled the ccp1 module does not assert control of the ccp1 pin in this mode (see the ccp1con register). the special event trigger output of the ccp occurs immediately upon a match between the tmr1h, tmr1l register pair and the ccpr1h, ccpr1l register pair. the tmr1h, tmr1l register pair is not reset until the next rising edge of the timer1 clock. this allows the ccpr1h, ccpr1l register pair to effectively provide a 16-bit programmable period register for timer1. note: clearing the ccp1con register will force the ccp1 compare output latch to the default low level. this is not the port i/o data latch. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set ccp1if interrupt flag (pir1) match tris ccp1con<3:0> mode select output enable pin special event trigger will: ? clear tmr1h and tmr1l registers. ? not set interrupt flag bit tmr1if of the pir1 register. ? set the go/done bit to start the adc conversion. ccp1 4 note 1: the special event trigger from the ccp module does not set interrupt flag bit tmr1if of the pir1 register. 2: removing the match condition by changing the contents of the ccpr1h and ccpr1l register pair, between the clock edge that generates the special event trigger and the clock edge that generates the timer1 reset, will preclude the reset from occurring.
? 2007 microchip technology inc. preliminary ds41288c-page 87 pic16f610/616/16hv610/616 table 10-3: summary of registers associated with compare name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on por, bor value on all other resets ccp1con (1) p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 ccpr1l (1) capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h (1) capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 ? adie (1) ccp1ie (1) c2ie c1ie ? tmr2ie (1) tmr1ie -000 0-00 0000 0-00 pir1 ? adif (1) ccp1if (1) c2if c1if ? tmr2if (1) tmr1if -000 0-00 0000 0-00 t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 trisc ? ?trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the capture, compare and pwm. note 1: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 88 preliminary ? 2007 microchip technology inc. 10.3 pwm mode the pwm mode generates a pulse-width modulated signal on the ccp1 pin. the duty cycle, period and resolution are determined by the following registers: ?pr2 ?t2con ? ccpr1l ? ccp1con in pulse-width modulation (pwm) mode, the ccp module produces up to a 10-bit resolution pwm output on the ccp1 pin. since the ccp1 pin is multiplexed with the port data latch, the tris for that pin must be cleared to make the ccp1 pin an output. figure 10-3 shows a simplified block diagram of pwm operation. figure 10-4 shows a typical waveform of the pwm signal. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 10.3.7 ?setup for pwm operation? . figure 10-3: simplified pwm block diagram the pwm output (figure 10-4) has a time base (period) and a time that the output stays high (duty cycle). figure 10-4: ccp pwm output note: clearing the ccp1con register will relinquish ccp1 control of the ccp1 pin. ccpr1l ccpr1h (2) (slave) comparator tmr2 pr2 (1) rq s duty cycle registers ccp1con<5:4> clear timer2, toggle ccp1 pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concatenated with the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. 2: in pwm mode, ccpr1h is a read-only register . tris ccp1 comparator period pulse width tmr2 = 0 tmr2 = ccpr1l:ccp1con<5:4> tmr2 = pr2
? 2007 microchip technology inc. preliminary ds41288c-page 89 pic16f610/616/16hv610/616 10.3.1 pwm period the pwm period is specified by writing to the pr2 register of timer2. the pwm period can be calculated using the formula of equation 10-1. equation 10-1: pwm period when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ? tmr2 is cleared ? the ccp1 pin is set. (exception: if the pwm duty cycle = 0%, the pin will not be set.) ? the pwm duty cycle is latched from ccpr1l into ccpr1h. 10.3.2 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to multiple registers: ccpr1l register and ccp1<1:0> bits of the ccp1con register. the ccpr1l contains the eight msbs and the ccp1<1:0> bits of the ccp1con register contain the two lsbs. ccpr1l and ccp1<1:0> bits of the ccp1con register can be written to at any time. the duty cycle value is not latched into ccpr1h until after the period completes (i.e., a match between pr2 and tmr2 registers occurs). while using the pwm, the ccpr1h register is read-only. equation 10-2 is used to calculate the pwm pulse width. equation 10-3 is used to calculate the pwm duty cycle ratio. equation 10-2: pulse width equation 10-3: duty cycle ratio the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. the 8-bit timer tmr2 register is concatenated with either the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2 prescaler is set to 1:1. when the 10-bit time base matches the ccpr1h and 2-bit latch, then the ccp1 pin is cleared (see figure 10-3). 10.3.3 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is 10 bits when pr2 is 255. the resolution is a function of the pr2 register value as shown by equation 10-4. equation 10-4: pwm resolution table 10-4: example pwm frequencies and resolutions (f osc = 20 mhz) table 10-5: example pwm frequencies and resolutions (f osc = 8 mhz) note: the timer2 postscaler (see section 7.1 ?timer2 operation? ) is not used in the determination of the pwm frequency. pwm period pr2 () 1 + [] 4t osc ? ? ? = (tmr2 prescale value) note: if the pulse width value is greater than the period the assigned pwm pin(s) will remain unchanged. pulse width ccpr1l:ccp1con<5:4> () ? = t osc ? (tmr2 prescale value) duty cycle ratio ccpr1l:ccp1con<5:4> () 4pr2 1 + () ----------------------------------------------------------------------- = resolution 4pr2 1 + () [] log 2 () log ----------------------------------------- - bits = pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5
pic16f610/616/16hv610/616 ds41288c-page 90 preliminary ? 2007 microchip technology inc. 10.3.4 operation in sleep mode in sleep mode, the tmr2 register will not increment and the state of the module will not change. if the ccp1 pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2 will continue from its previous state. 10.3.5 changes in system clock frequency the pwm frequency is derived from the system clock frequency. any changes in the system clock frequency will result in changes to the pwm frequency. see section 3.0 ?oscillator module? for additional details. 10.3.6 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. 10.3.7 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. configure the pwm pin (ccp1) as an input by setting the associated tris bit. 2. set the pwm period by loading the pr2 register. 3. configure the ccp module for the pwm mode by loading the ccp1con register with the appropriate values. 4. set the pwm duty cycle by loading the ccpr1l register and ccp1 bits of the ccp1con register. 5. configure and start timer2: ? clear the tmr2if interrupt flag bit of the pir1 register. ? set the timer2 prescale value by loading the t2ckps bits of the t2con register. ? enable timer2 by setting the tmr2on bit of the t2con register. 6. enable pwm output after a new pwm cycle has started: ? wait until timer2 overflows (tmr2if bit of the pir1 register is set). ? enable the ccp1 pin output by clearing the associated tris bit.
? 2007 microchip technology inc. preliminary ds41288c-page 91 pic16f610/616/16hv610/616 10.4 pwm (enhanced mode) the enhanced pwm mode can generate a pwm signal on up to four different output pins with up to 10-bits of resolution. it can do this through four different pwm output modes: ? single pwm ? half-bridge pwm ? full-bridge pwm, forward mode ? full-bridge pwm, reverse mode to select an enhanced pwm mode, the p1m bits of the ccp1con register must be set appropriately. the pwm outputs are multiplexed with i/o pins and are designated p1a, p1b, p1c and p1d. the polarity of the pwm pins is configurable and is selected by setting the ccp1m bits in the ccp1con register appropriately. table 10-6 shows the pin assignments for each enhanced pwm mode. figure 10-5 shows an example of a simplified block diagram of the enhanced pwm module. figure 10-5: example simplified block di agram of the enhanced pwm mode table 10-6: example pin assignments for various pwm enhanced modes note: to prevent the generation of an incomplete waveform when the pwm is first enabled, the eccp module waits until the start of a new pwm period before generating a pwm signal. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (1) rq s duty cycle registers ccp1<1:0> clear timer2, toggle pwm pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler to create the 10-bit time base. trisc<5> ccp1/p1a trisc<4> p1b trisc<3> p1c trisc<2> p1d output controller p1m<1:0> 2 ccp1m<3:0> 4 pwm1con ccp1/p1a p1b p1c p1d note 1: the tris register value for each pwm output must be configured appropriately. 2: clearing the ccp1con register will relinquish eccp control of all pwm output pins. 3: any pin not used by an enhanced pwm mode is available for alternate pin functions eccp mode p1m ccp1/p1a p1b p1c p1d single 00 yes no no no half-bridge 10 yes yes no no full-bridge, forward 01 yes yes yes yes full-bridge, reverse 11 yes yes yes yes
pic16f610/616/16hv610/616 ds41288c-page 92 preliminary ? 2007 microchip technology inc. figure 10-6: example pwm (enhanced mode) output relationships (active-high state) 0 period 00 10 01 11 signal pr2+1 p1m<1:0> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive pulse width (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: ? period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) ? pulse width = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) ? delay = 4 * t osc * (pwm1con<6:0>) note 1: dead-band delay is programmed using the pwm1con register ( section 10.4.6 ?programmable dead-band delay mode? ).
? 2007 microchip technology inc. preliminary ds41288c-page 93 pic16f610/616/16hv610/616 figure 10-7: example enhanced pwm output relationships (active-low state) 0 period 00 10 01 11 signal pr2+1 p1m<1:0> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive pulse width (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: ? period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) ? pulse width = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) ? delay = 4 * t osc * (pwm1con<6:0>) note 1: dead-band delay is programmed using the pwm1con register ( section 10.4.6 ?programmable dead-band delay mode? ).
pic16f610/616/16hv610/616 ds41288c-page 94 preliminary ? 2007 microchip technology inc. 10.4.1 half-bridge mode in half-bridge mode, two pins are used as outputs to drive push-pull loads. the pwm output signal is output on the ccp1/p1a pin, while the complementary pwm output signal is output on the p1b pin (see figure 10-8). this mode can be used for half-bridge applications, as shown in figure 10-9, or for full-bridge applications, where four power switches are being modulated with two pwm signals. in half-bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in half- bridge power devices. the value of the pdc<6:0> bits of the pwm1con register sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see 10.4.6 ?programmable dead-band delay mode? for more details of the dead-band delay operations. since the p1a and p1b outputs are multiplexed with the port data latches, the associated tris bits must be cleared to configure p1a and p1b as outputs. figure 10-8: example of half- bridge pwm output figure 10-9: example of half-bridge applications period pulse width td td (1) p1a (2) p1b (2) td = dead-band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high. p1a p1b fet driver fet driver load + - + - fet driver fet driver v+ load fet driver fet driver p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit
? 2007 microchip technology inc. preliminary ds41288c-page 95 pic16f610/616/16hv610/616 10.4.2 full-bridge mode in full-bridge mode, all four pins are used as outputs. an example of full-bridge application is shown in figure 10-10. in the forward mode, pin ccp1/p1a is driven to its active state, pin p1d is modulated, while p1b and p1c will be driven to their inactive state as shown in figure 10-11. in the reverse mode, p1c is driven to its active state, pin p1b is modulated, while p1a and p1d will be driven to their inactive state as shown figure 10-11. p1a, p1b, p1c and p1d outputs are multiplexed with the port data latches. the associated tris bits must be cleared to configure the p1a, p1b, p1c and p1d pins as outputs. figure 10-10: example of full-bridge application p1a p1c fet driver fet driver v+ v- load fet driver fet driver p1b p1d qa qb qd qc
pic16f610/616/16hv610/616 ds41288c-page 96 preliminary ? 2007 microchip technology inc. figure 10-11: example of full-bridge pwm output period pulse width p1a (2) p1b (2) p1c (2) p1d (2) forward mode (1) period pulse width p1a (2) p1c (2) p1d (2) p1b (2) reverse mode (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signal is shown as active-high.
? 2007 microchip technology inc. preliminary ds41288c-page 97 pic16f610/616/16hv610/616 10.4.2.1 direction change in full-bridge mode in the full-bridge mode, the p1m1 bit in the ccp1con register allows users to control the forward/reverse direction. when the application firmware changes this direction control bit, the module will change to the new direction on the next pwm cycle. a direction change is initiated in software by changing the p1m1 bit of the ccp1con register. the following sequence occurs four timer2 cycles prior to the end of the current pwm period: ? the modulated outputs (p1b and p1d) are placed in their inactive state. ? the associated unmodulated outputs (p1a and p1c) are switched to drive in the opposite direction. ? pwm modulation resumes at the beginning of the next period. see figure 10-12 for an illustration of this sequence. the full-bridge mode does not provide dead-band delay. as one output is modulated at a time, dead-band delay is generally not required. there is a situation where dead-band delay is required. this situation occurs when both of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. figure 10-13 shows an example of the pwm direction changing from forward to reverse, at a near 100% duty cycle. in this example, at time t1, the output p1a and p1d become inactive, while output p1c becomes active. since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices qc and qd (see figure 10-10) for the duration of ?t?. the same phenomenon will occur to power devices qa and qb for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. reduce pwm duty cycle for one pwm period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. other options to prevent shoot-through current may exist. figure 10-12: example of pwm direction change pulse width period (1) signal note 1: the direction bit p1m1 of the ccp1con register is written any time during the pwm cycle. 2: when changing directions, the p1a and p1c signals switch before the end of the current pwm cycle. the modulated p1b and p1d signals are inactive at this time. the length of this time is four timer2 counts. period (2) p1a (active-high) p1b (active-high) p1c (active-high) p1d (active-high) pulse width
pic16f610/616/16hv610/616 ds41288c-page 98 preliminary ? 2007 microchip technology inc. figure 10-13: example of pwm direct ion change at near 100% duty cycle forward period reverse period p1a t on t off t = t off ? t on p1b p1c p1d external switch d potential shoot-through current note 1: all signals are shown as active-high. 2: t on is the turn on delay of power switch qc and its driver. 3: t off is the turn off delay of pow er switch qd and its driver. external switch c t1 dc pw
? 2007 microchip technology inc. preliminary ds41288c-page 99 pic16f610/616/16hv610/616 10.4.3 start-up considerations when any pwm mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the pwm output pins. the ccp1m<1:0> bits of the ccp1con register allow the user to choose whether the pwm output signals are active-high or active-low for each pair of pwm output pins (p1a/p1c and p1b/p1d). the pwm output polarities must be selected before the pwm pins are configured as outputs. changing the polarity configuration while the pwm pins are configured as outputs is not recommended since it may result in damage to the application circuits. the p1a, p1b, p1c and p1d output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pins for output at the same time as the enhanced pwm modes may cause damage to the application circuit. the enhanced pwm modes must be enabled in the proper output mode and complete a full pwm cycle before configuring the pwm pins as outputs. the completion of a full pwm cycle is indicated by the tmr2if bit of the pir1 register being set as the second pwm period begins. note: when the microcontroller is released from reset, all of the i/o pins are in the high- impedance state. the external circuits must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels or activates the pwm output(s).
pic16f610/616/16hv610/616 ds41288c-page 100 preliminary ? 2007 microchip technology inc. 10.4.4 enhanced pwm auto- shutdown mode the pwm mode supports an auto-shutdown mode that will disable the pwm outputs when an external shutdown event occurs. auto-shutdown mode places the pwm output pins into a predetermined state. this mode is used to help prevent the pwm from damaging the application. the auto-shutdown sources are selected using the eccpasx bits of the eccpas register. a shutdown event may be generated by: ?a logic ? 0 ? on the int pin ? comparator c1 ? comparator c2 ? setting the eccpase bit in firmware a shutdown condition is indicated by the eccpase (auto-shutdown event status) bit of the eccpas register. if the bit is a ? 0 ?, the pwm pins are operating normally. if the bit is a ? 1 ?, the pwm outputs are in the shutdown state. when a shutdown event occurs, two things happen: the eccpase bit is set to ? 1 ?. the eccpase will remain set until cleared in firmware or an auto-restart occurs (see section 10.4.5 ?auto-restart mode? ). the enabled pwm pins are asynchronously placed in their shutdown states. the pwm output pins are grouped into pairs [p1a/p1c ] and [p1b/p1d]. the state of each pin pair is determined by the pssac and pssbd bits of the eccpas register. each pin pair may be placed into one of three states: ? drive logic ? 1 ? ? drive logic ? 0 ? ? tri-state (high-impedance) register 10-2: eccpas: enhanced capture/compare/pwm auto-shutdown control register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eccpase: eccp auto-shutdown event status bit 1 = a shutdown event has occurred; eccp outputs are in shutdown state 0 = eccp outputs are operating bit 6-4 eccpas<2:0>: eccp auto-shutdown source select bits 000 = auto-shutdown is disabled 001 = comparator c1 output high 010 = comparator c2 output high (1) 011 = either comparators output is high 100 =v il on int pin 101 =v il on int pin or comparator c1 output high 110 =v il on int pin or comparator c2 output high 111 =v il on int pin or either comparators output is high bit 3-2 pssacn: pins p1a and p1c shutdown state control bits 00 = drive pins p1a and p1c to ? 0 ? 01 = drive pins p1a and p1c to ? 1 ? 1x = pins p1a and p1c tri-state bit 1-0 pssbdn: pins p1b and p1d shutdown state control bits 00 = drive pins p1b and p1d to ? 0 ? 01 = drive pins p1b and p1d to ? 1 ? 1x = pins p1b and p1d tri-state
? 2007 microchip technology inc. preliminary ds41288c-page 101 pic16f610/616/16hv610/616 figure 10-14: pwm auto-shutdown with firmware restart (prsen = 0 ) 10.4.5 auto-restart mode the enhanced pwm can be configured to automati- cally restart the pwm signal once the auto-shutdown condition has been removed. auto-restart is enabled by setting the prsen bit in the pwm1con register. if auto-restart is enabled, the eccpase bit will remain set as long as the auto-shutdown condition is active. when the auto-shutdown condition is removed, the eccpase bit will be cleared via hardware and normal operation will resume. figure 10-15: pwm auto-shutdown with auto-restart enabled (prsen = 1 ) note 1: the auto-shutdown condition is a level- based signal, not an edge-based signal. as long as the level is present, the auto- shutdown will persist. 2: writing to the eccpase bit is disabled while an auto-shutdown condition persists. 3: once the auto-shutdown condition has been removed and the pwm restarted (either through firmware or auto-restart), the pwm signal will always restart at the beginning of the next pwm period. shutdown pwm eccpase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period eccpase cleared by firmware pwm period shutdown pwm eccpase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period pwm period
pic16f610/616/16hv610/616 ds41288c-page 102 preliminary ? 2007 microchip technology inc. 10.4.6 programmable dead-band delay mode in half-bridge applications where all power switches are modulated at the pwm frequency, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current ( shoot-through current ) will flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot- through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in half-bridge mode, a digitally programmable dead- band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 10-16 for illustration. the lower seven bits of the associated pwm1con register (register 10-3) sets the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). figure 10-16: example of half- bridge pwm output figure 10-17: example of half-bridge applications period pulse width td td (1) p1a (2) p1b (2) td = dead-band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high. p1a p1b fet driver fet driver v+ v- load + v - + v - standard half-bridge circuit (?push-pull?)
? 2007 microchip technology inc. preliminary ds41288c-page 103 pic16f610/616/16hv610/616 table 10-7: summary of registers associated with pwm register 10-3: pwm1con: enhanced pwm control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 prsen: pwm restart enable bit 1 = upon auto-shutdown, the eccpase bit clears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, eccpase must be cleared in software to restart the pwm bit 6-0 pdc<6:0>: pwm delay count bits pdcn = number of f osc /4 (4 * t osc ) cycles between the scheduled time when a pwm signal should transition active and the actual time it transitions active name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 value on por, bor value on all other resets ccp1con (1) p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 ccpr1l (1) capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h (1) capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu cm1con0 c1on c1out c1oe c1pol ? c1r c1ch1 c1ch0 0000 -000 0000 -000 cm2con0 c2on c2out c2oe c2pol ? c2r c2ch1 c2ch0 0000 -000 0000 -000 cm2con1 mc1out mc2out ? t1acs c1hys c2hys t1gss c2sync 00-0 0010 00-0 0010 eccpas (1) eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 0000 0000 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 ? adie (1) ccp1ie (1) c2ie c1ie ?tmr2ie (1) tmr1ie -000 0-00 0000 0-00 pir1 ? adif (1) ccp1if (1) c2if c1if ?tmr2if (1) tmr1if -000 0-00 0000 0-00 pwm1con (1) prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 0000 0000 0000 0000 t2con (1) ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 tmr2 (1) timer2 module register 0000 0000 0000 0000 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 trisc ? ? trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the capture, compare and pwm. note 1: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 104 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 105 pic16f610/616/16hv610/616 11.0 voltage regulator the pic16hv616 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the v dd pin. this eliminates the need for an external voltage regulator in systems sourced by an unregulated supply. all external devices connected directly to the v dd pin will share the regulated supply voltage and contribute to the total v dd supply current (i load ). 11.1 regulator operation a shunt regulator generates a specific supply voltage by creating a voltage drop across a pass resistor r ser . the voltage at the v dd pin of the microcontroller is monitored and compared to an internal voltage refer- ence. the current through the resistor is then adjusted, based on the result of the comparison, to produce a voltage drop equal to the difference between the supply voltage v unreg and the v dd of the microcontroller. see figure 11-1 for voltage regulator schematic. figure 11-1: voltage regulator an external current limiting resistor, r ser , located between the unregulated supply, v unreg , and the v dd pin, drops the difference in voltage between v unreg and v dd . r ser must be between r max and r min as defined by equation 11-1. equation 11-1: r ser limiting resistor 11.2 regulator considerations the supply voltage v unreg and load current are not constant. therefore, the current range of the regulator is limited. selecting a value for r ser must take these three factors into consideration. since the regulator uses the band gap voltage as the regulated voltage reference, this voltage reference is permanently enabled in the pic16f610/16hv610 devices. feedback v dd v ss c bypass r ser v unreg i supply i shunt i load r max = (vu min - 5v) 1.05 ? (4 m a + i load ) r min = (vu max - 5v) 0.95 ? (50 m a) where: r max = maximum value of r ser (ohms) r min = minimum value of r ser (ohms) vu min = minimum value of v unreg vu max = maximum value of v unreg v dd = regulated voltage (5v nominal) i load = maximum expected load current in ma including i/o pin currents and externa l circuits connected to v dd . 1.05 = compensation for +5% tolerance of r ser 0.95 = compensation for -5% tolerance of r ser
pic16f610/616/16hv610/616 ds41288c-page 106 preliminary ? 2007 microchip technology inc. 12.0 special features of the cpu the pic16f610/616/16hv610/616 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. these features are: ?reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? oscillator selection ? sleep ? code protection ? id locations ? in-circuit serial programming the pic16f610/616/16hv610/616 has two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. there is also circuitry to reset the device if a brown-out occurs, which can use the power- up timer to provide at least a 64 ms reset. with these three functions-on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low-current power-down mode. the user can wake-up from sleep through: ? external reset ? watchdog timer wake-up ? an interrupt several oscillator options are also made available to allow the part to fit the application. the intosc option saves system cost while the lp crystal option saves power. a set of configuration bits are used to select various options (see register 12-1). 12.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?) to select various device configurations as shown in register 12-1. these bits are mapped in program memory location 2007h. note: address 2007h is beyond the user program memory space. it belongs to the special configuration memory space (2000h- 3fffh), which can be accessed only during programming. see ?pic12f60x/12f61x/ 16f61x memory programming specifica- tion? (ds41284) for more information.
? 2007 microchip technology inc. preliminary ds41288c-page 107 pic16f610/616/16hv610/616 register 12-1: config: co nfiguration word register ? ? ? ? ? ?boren1 (1) boren0 (1) bit 15 bit 8 ioscfs cp (2) mclre (3) pwrte wdte fosc2 fosc1 fosc0 bit 7 bit 0 legend: r = readable bit w = writable bit p = programmable? u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-10 unimplemented : read as ? 1 ? bit 9-8 boren<1:0>: brown-out reset selection bits (1) 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 0x = bor disabled bit 7 ioscfs: internal oscillator frequency select bit 1 = 8 mhz 0 = 4 mhz bit 6 cp : code protection bit (2) 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 5 mclre: mclr pin function select bit (3) 1 = mclr pin function is mclr 0 = mclr pin function is digital input, mclr internally tied to v dd bit 4 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0 fosc<2:0>: oscillator selection bits 111 = rc oscillator: clkout function on ra4/osc2/clkout pin, rc on ra5/osc1/clkin 110 = rcio oscillator: i/o function on ra4/osc2/clkout pin, rc on ra5/osc1/clkin 101 = intosc oscillator: clkout function on ra4/osc2/clkout pin, i/o function on ra5/osc1/clkin 100 = intoscio oscillator: i/o function on ra4/osc2/clkout pin, i/o function on ra5/osc1/clkin 011 = ec: i/o function on ra4/osc2/clkout pin, clkin on ra5/osc1/clkin 010 = hs oscillator: high-speed crystal/resonat or on ra4/osc2/clkout and ra5/osc1/clkin 001 = xt oscillator: crystal/resonator on ra4/osc2/clkout and ra5/osc1/clkin 000 = lp oscillator: low-power crystal on ra4/osc2/clkout and ra5/osc1/clkin note 1: enabling brown-out reset does not automatically enable power-up timer. 2: the entire program memory will be erased when the code protection is turned off. 3: when mclr is asserted in intosc or rc mode, the internal clock oscillator is disabled.
pic16f610/616/16hv610/616 ds41288c-page 108 preliminary ? 2007 microchip technology inc. 12.2 calibration bits the 8 mhz internal oscillator is factory calibrated. these calibration values are stored in fuses located in the calibration word (2009h). the calibration word is not erased when using the specified bulk erase sequence in the ?pic12f60x/12f61x/16f61x memory programming specification? (ds41284) and thus, does not require reprogramming. 12.3 reset the pic16f610/616/16hv610/616 differentiates between various kinds of reset: a) power-on reset (por) b) wdt reset during normal operation c) wdt reset during sleep d) mclr reset during normal operation e) mclr reset during sleep f) brown-out reset (bor) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on: ? power-on reset ?mclr reset ?mclr reset during sleep ? wdt reset ? brown-out reset (bor) wdt wake-up does not cause register resets in the same manner as a wdt reset since wake-up is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations, as indicated in table 12-2. software can use these bits to determine the nature of the reset. see table 12-4 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 12-1. the mclr reset path has a noise filter to detect and ignore small pulses. see section 15.0 ?electrical specifications? for pulse-width specifications. figure 12-1: simplified block diagram of on-chip reset circuit s rq external reset mclr /v pp pin v dd osc1/ wdt module por detect ost/pwrt on-chip wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter reset enable ost enable pwrt sleep brown-out (1) reset boren clki pin note 1: refer to the configuration word register (register 12-1). rc osc
? 2007 microchip technology inc. preliminary ds41288c-page 109 pic16f610/616/16hv610/616 12.3.1 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper operation. to take advantage of the por, simply connect the mclr pin through a resistor to v dd . this will eliminate external rc components usually needed to create power-on reset. a maximum rise time for v dd is required. see section 15.0 ?electrical specifications? for details. if the bor is enabled, the maximum rise time specification does not apply. the bor circuitry will keep the device in reset until v dd reaches v bor (see section 12.3.4 ?brown-out reset (bor)? ). when the device starts normal operation (exits the reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure proper operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 12.3.2 mclr pic16f610/616/16hv610/616 has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. voltages applied to the mclr pin that exceed its specification can result in both mclr resets and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 12-2, is suggested. an internal mclr option is enabled by clearing the mclre bit in the configuration word register. when mclre = 0 , the reset signal to the chip is generated internally. when the mclre = 1 , the ra3/mclr pin becomes an external reset input. in this mode, the ra3/mclr pin has a weak pull-up to v dd . figure 12-2: recommended mclr circuit 12.3.3 power-up timer (pwrt) the power-up timer provides a fixed 64 ms (nominal) time-out on power-up only, from por or brown-out reset. the power-up timer operates from an internal rc oscillator. for more information, see section 3.4 ?internal clock modes? . the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a configuration bit, pwrte , can disable (if set) or enable (if cleared or programmed) the power-up timer. the power-up timer should be enabled when brown-out reset is enabled, although it is not required. the power-up timer delay will vary from chip-to-chip due to: ?v dd variation ? temperature variation ? process variation see dc parameters for details ( section 15.0 ?electrical specifications? ). note: the por circuit does not produce an internal reset when v dd declines. to re- enable the por, v dd must reach vss for a minimum of 100 s. note: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resis- tor of 50-100 should be used when applying a ?low? level to the mclr pin, rather than pulling this pin directly to v ss . v dd pic ? mcu mclr r1 1k ( or greater) c1 0.1 f (optional, not critical) r2 100 ( needed with capacitor) sw1 (optional)
pic16f610/616/16hv610/616 ds41288c-page 110 preliminary ? 2007 microchip technology inc. 12.3.4 brown-out reset (bor) the boren0 and boren1 bits in the configuration word register select one of three bor modes. selecting boren<1:0> = 10 , the bor is automatically disabled in sleep to conserve power and enabled on wake-up. see register 12-1 for the configuration word definition. a brown-out occurs when v dd falls below v bor for greater than parameter t bor (see section 15.0 ?electrical specifications? ). the brown-out condition will reset the device. this will occur regardless of v dd slew rate. a brown-out reset may not occur if v dd falls below v bor for less than parameter t bor . on any reset (power-on, brown-out reset, watchdog timer, etc.), the chip will remain in reset until v dd rises above v bor (see figure 12-3). if enabled, the power- up timer will be invoked by the reset and keep the chip in reset an additional 64 ms. if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above v bor , the power-up timer will execute a 64 ms reset. figure 12-3: brown-out situations note: the power-up timer is enabled by the pwrte bit in the configuration word register. 64 ms (1) v bor v dd internal reset v bor v dd internal reset 64 ms (1) < 64 ms 64 ms (1) v bor v dd internal reset note 1: 64 ms delay only if pwrte bit is programmed to ? 0 ?.
? 2007 microchip technology inc. preliminary ds41288c-page 111 pic16f610/616/16hv610/616 12.3.5 time-out sequence on power-up, the time-out sequence is as follows: ? pwrt time-out is invoked after por has expired. ? ost is activated after the pwrt time-out has expired. the total time-out will vary based on oscillator configuration and pwrte bit status. for example, in ec mode with pwrte bit erased (pwrt disabled), there will be no time-out at all. figure 12-4, figure 12-5 and figure 12-6 depict time-out sequences. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then, bringing mclr high will begin execution immediately (see figure 12-5). this is useful for testing purposes or to synchronize more than one pic16f610/616/ 16hv610/616 device operating in parallel. table 12-5 shows the reset conditions for some special registers, while table 12-4 shows the reset conditions for all the registers. 12.3.6 power control (pcon) register the power control register pcon (address 8eh) has two status bits to indicate what type of reset occurred last. bit 0 is bor (brown-out). bor is unknown on power- on reset. it must then be set by the user and checked on subsequent resets to see if bor = 0 , indicating that a brown-out has occurred. the bor status bit is a ?don?t care? and is not necessarily predictable if the brown-out circuit is disabled (boren<1:0> = 00 in the configuration word register). bit 1 is por (power-on reset). it is a ? 0 ? on power-on reset and unaffected otherwise. the user must write a ? 1 ? to this bit following a power-on reset. on a subse- quent reset, if por is ? 0 ?, it will indicate that a power- on reset has occurred (i.e., v dd may have gone too low). for more information, see section 12.3.4 ?brown-out reset (bor)? . table 12-1: time-out in various situations table 12-2: status/pcon bits and their significance table 12-3: summary of registers associated with brown-out reset oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024 ? t osc 1024 ? t osc t pwrt + 1024 ? t osc 1024 ? t osc 1024 ? t osc rc, ec, intosc t pwrt ?t pwrt ?? por bor to pd condition 0x11 power-on reset u011 brown-out reset uu0u wdt reset uu00 wdt wake-up uuuu mclr reset during normal operation uu10 mclr reset during sleep legend: u = unchanged, x = unknown name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets (1) pcon ? ? ? ? ? ?por bor ---- --qq ---- --uu status irp rp1 rp0 to pd z dc c 0001 1xxx 000q quuu legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. shaded cells are not used by bor. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation.
pic16f610/616/16hv610/616 ds41288c-page 112 preliminary ? 2007 microchip technology inc. figure 12-4: time-out sequence on power-up (delayed mclr ): case 1 figure 12-5: time-out sequence on power-up (delayed mclr ): case 2 figure 12-6: time-out sequence on power-up (mclr with v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt
? 2007 microchip technology inc. preliminary ds41288c-page 113 pic16f610/616/16hv610/616 table 12-4: initialization condition for registers register address power-on reset mclr reset wdt reset brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt time-out w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h/82h 0000 0000 0000 0000 pc + 1 (3) status 03h/83h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h --x0 x000 --u0 u000 --uu uuuu portc 07h --xx xx00 --uu 00uu --uu uuuu pclath 0ah/8ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh/8bh 0000 0000 0000 0000 uuuu uuuu (2) pir1 0ch -000 0-00 -000 0-00 -uuu u-uu (2) tmr1l 0eh xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 0fh xxxx xxxx uuuu uuuu uuuu uuuu t1con 10h 0000 0000 uuuu uuuu -uuu uuuu tmr2 (6) 11h 0000 0000 0000 0000 uuuu uuuu t2con (6) 12h -000 0000 -000 0000 -uuu uuuu ccpr1l (6) 13h xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h (6) 14h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con (6) 15h 0000 0000 0000 0000 uuuu uuuu pwm1con (6) 16h 0000 0000 0000 0000 uuuu uuuu eccpas (6) 17h 0000 0000 0000 0000 uuuu uuuu vrcon 19h 0000 0000 0000 0000 uuuu uuuu cm1con0 1ah 0000 -000 0000 -000 uuuu -uuu cm2con0 1bh 0000 -000 0000 -000 uuuu -uuu cm2con1 1ch 00-0 0000 00-0 0000 uu-u uuuu adresh (6) 1eh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 (6) 1fh 0000 0000 0000 0000 uuuu uuuu option_reg 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h --11 1111 --11 1111 --uu uuuu trisc 87h --11 1111 --11 1111 --uu uuuu pie1 8ch -000 0-00 -000 0-00 -uuu u-uu pcon 8eh ---- --0x ---- --uu (1, 5) ---- --uu osctune 90h ---0 0000 ---u uuuu ---u uuuu legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 12-5 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u . 6: PIC16F616/16hv616 only.
pic16f610/616/16hv610/616 ds41288c-page 114 preliminary ? 2007 microchip technology inc. table 12-5: initialization condition for special registers ansel 91h 1111 1111 1111 1111 uuuu uuuu pr2 (6) 92h 1111 1111 1111 1111 1111 1111 wpua 95h --11 -111 --11 -111 --uu -uuu ioca 96h --00 0000 --00 0000 --uu uuuu srcon0 99h 0000 00-0 0000 00-0 uuuu uu-u srcon1 9ah 00-- ---- 00-- ---- uu-- ---- adresl (6) 9eh xxxx xxxx uuuu uuuu uuuu uuuu adcon1 (6) 9fh -000 ---- -000 ---- -uuu ---- condition program counter status register pcon register power-on reset 000h 0001 1xxx ---- --0x mclr reset during normal operation 000h 000u uuuu ---- --uu mclr reset during sleep 000h 0001 0uuu ---- --uu wdt reset 000h 0000 uuuu ---- --uu wdt wake-up pc + 1 uuu0 0uuu ---- --uu brown-out reset 000h 0001 1uuu ---- --10 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---- --uu legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global interrupt enable bit, gie, is set, the pc is loaded with the interrupt vector (0004h) after execution of pc + 1. table 12-4: initialization condition for registers (continued) register address power-on reset mclr reset wdt reset (continued) brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt time-out (continued) legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 12-5 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u . 6: PIC16F616/16hv616 only.
? 2007 microchip technology inc. preliminary ds41288c-page 115 pic16f610/616/16hv610/616 12.4 interrupts the pic16f610/616/16hv610/616 has multiple sources of interrupt: ? external interrupt ra2/int ? timer0 overflow interrupt ? porta change interrupts ? 2 comparator interrupts ? a/d interrupt (PIC16F616/16hv616 only) ? timer1 overflow interrupt ? timer2 match interrupt (PIC16F616/16hv616 only) ? enhanced ccp interrupt (PIC16F616/16hv616 only) the interrupt control register (intcon) and peripheral interrupt request register 1 (pir1) record individual interrupt requests in flag bits. the intcon register also has individual and global interrupt enable bits. the global interrupt enable bit, gie of the intcon register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in the intcon register and pie1 register. gie is cleared on reset. when an interrupt is serviced, the following actions occur automatically: ? the gie is cleared to disable any further interrupt. ? the return address is pushed onto the stack. ? the pc is loaded with 0004h. the return from interrupt instruction, retfie , exits the interrupt routine, as well as sets the gie bit, which re-enables unmasked interrupts. the following interrupt flags are contained in the intcon register: ? int pin interrupt ? porta change interrupt ? timer0 overflow interrupt the peripheral interrupt flags are contained in the special register, pir1. the corresponding interrupt enable bit is contained in special register, pie1. the following interrupt flags are contained in the pir1 register: ? a/d interrupt ? 2 comparator interrupts ? timer1 overflow interrupt ? timer2 match interrupt ? enhanced ccp interrupt for external interrupt events, such as the int pin or porta change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends upon when the interrupt event occurs (see figure 12-8). the latency is the same for one or two- cycle instructions. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. for additional information on timer1, timer2, comparators, adc, enhanced ccp modules, refer to the respective peripheral section. 12.4.1 ra2/int interrupt the external interrupt on the ra2/int pin is edge- triggered; either on the rising edge if the intedg bit of the option register is set, or the falling edge, if the intedg bit is clear. when a valid edge appears on the ra2/int pin, the intf bit of the intcon register is set. this interrupt can be disabled by clearing the inte control bit of the intcon register. the intf bit must be cleared by software in the interrupt service routine before re-enabling this interrupt. the ra2/int interrupt can wake-up the processor from sleep, if the inte bit was set prior to going into sleep. see section 12.7 ?power-down mode (sleep)? for details on sleep and figure 12-9 for timing of wake-up from sleep through ra2/int interrupt. note 1: individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the interrupts, which were ignored, are still pending to be serviced when the gie bit is set again. note: the ansel register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ? and cannot generate an interrupt.
pic16f610/616/16hv610/616 ds41288c-page 116 preliminary ? 2007 microchip technology inc. 12.4.2 timer0 interrupt an overflow (ffh 00h) in the tmr0 register will set the t0if bit of the intcon register. the interrupt can be enabled/disabled by setting/clearing t0ie bit of the intcon register. see section 5.0 ?timer0 module? for operation of the timer0 module. 12.4.3 porta interrupt-on-change an input change on porta sets the raif bit of the intcon register. the interrupt can be enabled/ disabled by setting/clearing the raie bit of the intcon register. plus, individual pins can be configured through the ioca register. figure 12-7: interrupt logic note: if a change on the i/o pin should occur when any porta operation is being executed, then the raif interrupt flag may not get set. tmr1if tmr1ie c1if c1ie t0if t0ie intf inte raif raie gie peie wake-up (if in sleep mode) (1) interrupt to cpu adif (2) adie (2) ioc-ra0 ioca0 ioc-ra1 ioca1 ioc-ra2 ioca2 ioc-ra3 ioca3 ioc-ra4 ioca4 ioc-ra5 ioca5 tmr2if (2) tmr2ie (2) ccp1if (2) ccp1ie (2) c2if c2ie note 1: some peripherals depend upon the system clock for operation. since the system clock is suspended during sleep, only those peripherals which do not depend upon the system clock will wake the part from sleep. see section 12.7.1 ?wake-up from sleep? . 2: PIC16F616/16hv616 only.
? 2007 microchip technology inc. preliminary ds41288c-page 117 pic16f610/616/16hv610/616 figure 12-8: int pin interrupt timing table 12-6: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 ioca ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 --00 0000 --00 0000 pir1 ?adif (1) ccp1if (1) c2if c1if ?tmr2if (1) tmr1if -000 0-00 -000 0-00 pie1 ?adie (1) ccp1ie (1) c2ie c1ie ?tmr2ie (1) tmr1ie -000 0-00 -000 0-00 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends upon condition. shaded cells are not used by the interrupt module. note 1: PIC16F616/16hv616 only. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon reg.) gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-4 t cy . synchronous latency = 3 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in intosc and rc oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 15.0 ?electrical specifications? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1)
pic16f610/616/16hv610/616 ds41288c-page 118 preliminary ? 2007 microchip technology inc. 12.5 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt (e.g., w and status registers). this must be implemented in software. temporary holding registers w_temp and status_temp should be placed in the last 16 bytes of gpr (see figure 2-4). these 16 locations are common to all banks and do not require banking. this makes context save and restore operations simpler. the code shown in example 12-1 can be used to: ? store the w register ? store the status register ? execute the isr code ? restore the status (and bank select bit register) ? restore the w register example 12-1: saving status and w registers in ram note: the pic16f610/616/16hv610/616 does not require saving the pclath. however, if computed goto? s are used in both the isr and the main code, the pclath must be saved and restored in the isr. movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w ;swaps are used because they do not affect the status bits movwf status_temp ;save status to bank zero status_temp register : :(isr) ;insert user code here : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 2007 microchip technology inc. preliminary ds41288c-page 119 pic16f610/616/16hv610/616 12.6 watchdog timer (wdt) the watchdog timer is a free running, on-chip rc oscillator, which requires no external components. this rc oscillator is separate from the external rc oscillator of the clkin pin and intosc. that means that the wdt will run, even if the clock on the osc1 and osc2 pins of the device has been stopped (for example, by execution of a sleep instruction). during normal oper- ation, a wdt time out generates a device reset. if the device is in sleep mode, a wdt time out causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by program- ming the configuration bit, wdte, as clear ( section 12.1 ?configuration bits? ). 12.6.1 wdt period the wdt has a nominal time-out period of 18 ms (with no prescaler). the time-out periods vary with temperature, v dd and process variations from part to part (see table 15-4, parameter 31). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the prescaler, if assigned to the wdt, and prevent it from timing out and generating a device reset. the to bit in the status register will be cleared upon a watchdog timer time out. 12.6.2 wdt programming considerations it should also be taken in account that under worst- case conditions (i.e., v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt time out occurs. figure 12-2: watchdog timer block diagram table 12-7: wdt status conditions wdt wdte = 0 cleared clrwdt command exit sleep + system clock = extrc, intrc, ec exit sleep + system clock = xt, hs, lp cleared until the end of ost t0cki t0se pin clkout tmr0 watchdog timer wdt time-out ps<2:0> wdte data bus set flag bit t0if on overflow t0cs note 1: t0se, t0cs, psa, ps<2:0> are bits in the option register. 0 1 0 1 0 1 sync 2 cycles 8 8 8-bit prescaler 0 1 (= f osc /4) psa psa psa 3
pic16f610/616/16hv610/616 ds41288c-page 120 preliminary ? 2007 microchip technology inc. table 12-8: summary of registers associated with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 config (1) ioscfs cp mclre pwrte wdte fosc2 fosc1 fosc0 ? ? legend: shaded cells are not used by the watchdog timer. note 1: see register 12-1 for operation of all configuration word register bits.
? 2007 microchip technology inc. preliminary ds41288c-page 121 pic16f610/616/16hv610/616 12.7 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. if the watchdog timer is enabled: ? wdt will be cleared but keeps running. ?pd bit in the status register is cleared. ?to bit is set. ? oscillator driver is turned off. ? i/o ports maintain the status they had before sleep was executed (driving high, low or high-impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd or v ss , with no external circuitry drawing current from the i/o pin and the comparators and cv ref should be disabled. i/o pins that are high- impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull- ups on porta should be considered. the mclr pin must be at a logic high level. 12.7.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin. 2. watchdog timer wake-up (if wdt was enabled). 3. interrupt from ra2/int pin, porta change or a peripheral interrupt. the first event will cause a device reset. the two latter events are considered a continuation of program execution. the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. to bit is cleared if wdt wake-up occurred. the following peripheral interrupts can wake the device from sleep: 1. timer1 interrupt. timer1 must be operating as an asynchronous counter. 2. eccp capture mode interrupt. 3. a/d conversion (when a/d clock source is rc). 4. comparator output changes state. 5. interrupt-on-change. 6. external interrupt from int pin. other peripherals cannot generate interrupts since during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction, then branches to the interrupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. 12.7.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt prescaler and postscaler (if enabled) will not be cleared, the to bit will not be set and the pd bit will not be cleared. ? if the interrupt occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction is executed. therefore, the wdt and wdt prescaler and postscaler (if enabled) will be cleared, the to bit will be set and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction. see figure 12-9 for more details. note: it should be noted that a reset generated by a wdt time-out does not drive mclr pin low. note: if the global interrupts are disabled (gie is cleared) and any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set, the device will immediately wake-up from sleep.
pic16f610/616/16hv610/616 ds41288c-page 122 preliminary ? 2007 microchip technology inc. figure 12-9: wake-up from sleep through interrupt 12.8 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out using icsp ? for verification purposes. 12.9 id locations four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify mode. only the least significant 7 bits of the id locations are used. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon reg.) gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc ? 1) inst(pc + 1) sleep processor in sleep interrupt latency (3) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc + 2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024 t osc (drawing not to scale). this delay does not apply to ec, intosc and rc oscillator modes. 3: gie = ? 1 ? assumed. in this case after wake-up, the processor jumps to 0004h. if gie = ? 0 ?, execution will continue in-line. 4: clkout is not available in xt, hs, lp or ec oscillator modes, but shown here for timing reference. note: the entire flash program memory will be erased when the code protection is turned off. see the ?pic12f60x/12f61x/16f61x memory programming specification? (ds41284) for more information.
? 2007 microchip technology inc. preliminary ds41288c-page 123 pic16f610/616/16hv610/616 12.10 in-circuit serial programming? the pic16f610/616/16hv610/616 microcontrollers can be serially programmed while in the end application circuit. this is simply done with five connections for: ?clock ?data ? power ? ground ? programming voltage this allows customers to manufacture boards with unprogrammed devices and then program the micro- controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. the device is placed into a program/verify mode by holding the ra0 and ra1 pins low, while raising the mclr (v pp ) pin from v il to v ihh . see the ?pic12f60x/ 12f61x/16f61x memory programming specification? (ds41284) for more information. ra0 becomes the programming data and ra1 becomes the programming clock. both ra0 and ra1 are schmitt trigger inputs in program/verify mode. a typical in-circuit serial programming connection is shown in figure 12-10. figure 12-10: typical in-circuit serial programming connection 12.11 in-circuit debugger since in-circuit debugging requires access to three pins, mplab ? icd 2 development with an 14-pin device is not practical. a special 28-pin pic16f610/ 616/16hv610/616 icd device is used with mplab icd 2 to provide separate clock, data and mclr pins and frees all normally available pins to the user. a special debugging adapter allows the icd device to be used in place of a pic16f610/616/16hv610/616 device. the debugging adapter is the only source of the icd device. when the icd pin on the pic16f610/616/16hv610/ 616 icd device is held low, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab icd 2. when the microcontroller has this feature enabled, some of the resources are not available for general use. table 12-9 shows which features are consumed by the background debugger. table 12-9: debugger resources for more information, see ? mplab ? icd 2 in-circuit debugger user?s guide? (ds51331), available on microchip?s web site (www.microchip.com). figure 12-11: 28-pin icd pinout note: to erase, the device v dd must be above the bulk erase v dd minimum given in the ? pic12f615/12hv615/16f616/16hv616 memory programming specification? (ds41284) external connector signals to n o r m a l connections to n o r m a l connections pic16f610/16hv610 v dd v ss mclr /v pp /ra3 ra1 ra0 +5v 0v v pp clk data i/o * * * * * isolation devices (as required) PIC16F616/16hv616 resource description i/o pins icdclk, icddata stack 1 level program memory address 0h must be nop 700h-7ffh 28-pin pdip PIC16F616-icd in-circuit debug device v dd cs0 cs1 cs2 ra5 ra4 gnd ra0 ra1 shunten rc3 nc ra2 rc0 ra3 rc5 rc4 rc1 rc2 nc 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 icddata icd nc icdclk icdmclr nc nc nc 11 12 13 14 18 17 16 15
pic16f610/616/16hv610/616 ds41288c-page 124 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 125 pic16f610/616/16hv610/616 13.0 instruction set summary the pic16f610/616/16hv610/616 instruction set is highly orthogonal and is comprised of three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the formats for each of the categories is presented in figure 13-1, while the various opcode fields are summarized in table 13-1. table 13-2 lists the instructions recognized by the mpasm tm assembler. for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the w register. if ?d? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator, which selects the bit affected by the operation, while ?f? represents the address of the file in which the bit is located. for literal and control operations, ?k? represents an 8-bit or 11-bit constant, or literal value. one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 13.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (rmw) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a clrf porta instruction will read porta, clear all the data bits, then write the result back to porta. this example would have the unintended consequence of clearing the condition that set the raif flag. table 13-1: opcode field descriptions figure 13-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
pic16f610/616/16hv610/616 ds41288c-page 126 preliminary ? 2007 microchip technology inc. table 13-2: pic16f610/616/16hv610/616 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z z z z c c c, dc, z z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1, 2 1, 2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k ? k k k ? k ? ? k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c, dc, z z to , pd z to , pd c, dc, z z note 1: when an i/o register is modified as a function of itself (e.g., movf porta, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if the program counter (pc) is modified, or a conditional te st is true, the instruction requires two cycles. the second cycle is executed as a nop .
? 2007 microchip technology inc. preliminary ds41288c-page 127 pic16f610/616/16hv610/616 13.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b? in register ?f? is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a two-cycle instruction.
pic16f610/616/16hv610/616 ds41288c-page 128 preliminary ? 2007 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a two-cycle instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f ) (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f) - 1 (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2007 microchip technology inc. preliminary ds41288c-page 129 pic16f610/616/16hv610/616 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f) + 1 (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a two-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
pic16f610/616/16hv610/616 ds41288c-page 130 preliminary ? 2007 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f) (dest) status affected: z description: the contents of register ?f? is moved to a destination dependent upon the status of ?d?. if d = 0 , destination is w register. if d = 1 , the destination is file register ?f? itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w= value in fsr register z= 1 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assemble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w= 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movw f option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop
? 2007 microchip technology inc. preliminary ds41288c-page 131 pic16f610/616/16hv610/616 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table done call table;w contains ;table offset ;value goto done ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ;end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction.
pic16f610/616/16hv610/616 ds41288c-page 132 preliminary ? 2007 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. register f c register f c sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. result condition c = 0 w > k c = 1 w k dc = 0 w<3:0> > k<3:0> dc = 1 w<3:0> k<3:0>
? 2007 microchip technology inc. preliminary ds41288c-page 133 pic16f610/616/16hv610/616 subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f) - (w) ( destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. c = 0 w > f c = 1 w f dc = 0 w<3:0> > f<3:0> dc = 1 w<3:0> f<3:0> xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [ 0 , 1 ] operation: (w) .xor. (f) ( destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16f610/616/16hv610/616 ds41288c-page 134 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 135 pic16f610/616/16hv610/616 14.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 14.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic16f610/616/16hv610/616 ds41288c-page 136 preliminary ? 2007 microchip technology inc. 14.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 14.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcontrol- lers and the dspic30 and dspic33 family of digital sig- nal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 14.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 14.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 14.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2007 microchip technology inc. preliminary ds41288c-page 137 pic16f610/616/16hv610/616 14.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 14.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc ? and mcu devices. it debugs and programs pic ? and dspic ? flash microcontrollers with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 14.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 14.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic16f610/616/16hv610/616 ds41288c-page 138 preliminary ? 2007 microchip technology inc. 14.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 14.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 14.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits.
? 2007 microchip technology inc. preliminary ds41288c-page 139 pic16f610/616/16hv610/616 15.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. .........-40 to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss ................................................................................................... -0.3v to +6.5v voltage on mclr with respect to vss ............................................................................................... -0.3v to +1 3.5v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin ...................................................................................................................... 95 m a maximum current into v dd pin ......................................................................................................................... 9 5 ma input clamp current, i ik (v i < 0 or v i > v dd ) ............................................................................................................... 20 ma output clamp current, i ok (vo < 0 or vo >v dd ) ......................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma maximum current sunk by porta and portc (combined) ........................................................................... 9 0 ma maximum current sourced porta and portc (combined) ........................................................................... 9 0 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v o l x i ol ). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability.
pic16f610/616/16hv610/616 ds41288c-page 140 preliminary ? 2007 microchip technology inc. figure 15-1: pic16f610/616 voltage-frequency graph, -40c t a +125c figure 15-2: pic16hv610/616 voltage-frequency graph, -40c t a +125c 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 frequency (mhz) v dd (v) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 820 10 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 frequency (mhz) v dd (v) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 820 10
? 2007 microchip technology inc. preliminary ds41288c-page 141 pic16f610/616/16hv610/616 figure 15-3: pic16f610/616 voltage-frequency graph, -40c t a +125c figure 15-4: pic16hv610/616 voltage-frequency graph, -40c t a +125c 125 25 2.0 0 60 85 v dd (v) 4.0 5.0 4.5 temperature ( c ) 2.5 3.0 3.5 5.5 1% 2% 5% 125 25 2.0 0 60 85 v dd (v) 4.0 5.0 4.5 temperature ( c ) 2.5 3.0 3.5 1% 2% 5%
pic16f610/616/16hv610/616 ds41288c-page 142 preliminary ? 2007 microchip technology inc. 15.1 dc characteristics: pic16f610/616/16hv610/616-i (industrial) pic16f610/616/16hv610/616-e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions v dd supply voltage d001 pic16f610/616 2.0 ? 5.5 v f osc < = 4 mhz d001 pic16hv610/616 2.0 ? 5.0 v f osc < = 4 mhz d001b pic16f610/616 2.0 ? 5.5 v f osc < = 8 mhz d001b pic16hv610/616 2.0 ? 5.0 v f osc < = 8 mhz d001c pic16f610/616 3.0 ? 5.5 v f osc < = 10 mhz d001c pic16hv610/616 3.0 ? 5.0 v f osc < = 10 mhz d001d pic16f610/616 4.5 ? 5.5 v f osc < = 20 mhz d001d pic16hv610/616 4.5 ? 5.0 v f osc < = 20 mhz d002* v dr ram data retention voltage (1) 1.5 ? ? v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ?v ss ?vsee section 12.3.1 ?power-on reset (por)? for details. d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 12.3.1 ?power-on reset (por)? for details. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data.
? 2007 microchip technology inc. preliminary ds41288c-page 143 pic16f610/616/16hv610/616 15.2 dc characteristics: pic16f610/616/16hv610/616-i (industrial) pic16f610/616/16hv610/616-e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device characteristics min typ? max units conditions v dd note d010 supply current (i dd ) (1, 2) ?11 16 a2.0f osc = 32 khz lp oscillator mode ?18 28 a3.0 ?35 54 a5.0 d011* ? 140 240 a2.0f osc = 1 mhz xt oscillator mode ? 220 380 a3.0 ? 380 550 a5.0 d012 ? 260 360 a2.0f osc = 4 mhz xt oscillator mode ? 420 650 a3.0 ? 0.8 1.1 ma 5.0 d013* ? 130 220 a2.0f osc = 1 mhz ec oscillator mode ? 215 360 a3.0 ? 360 520 a5.0 d014 ? 220 340 a2.0f osc = 4 mhz ec oscillator mode ? 375 550 a3.0 ? 0.65 1.0 ma 5.0 d016* ? 340 450 a2.0f osc = 4 mhz intosc mode ? 500 700 a3.0 ? 0.8 1.2 ma 5.0 d017 ? 410 650 a2.0f osc = 8 mhz intosc mode ? 700 950 a3.0 ? 1.30 1.65 ma 5.0 d018 ? 230 400 a2.0f osc = 4 mhz extrc mode (3) ? 400 680 a3.0 ? 0.63 1.1 ma 5.0 d019 ? 2.6 3.25 ma 4.5 f osc = 20 mhz hs oscillator mode ? 2.8 3.35 ma 5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k .
pic16f610/616/16hv610/616 ds41288c-page 144 preliminary ? 2007 microchip technology inc. 15.3 dc characteristics: PIC16F616/16hv616- i (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device characteristics min typ? max units conditions v dd note d020 power-down base current(i pd ) (2) ? 0.05 1.2 a 2.0 wdt, bor, comparators, v ref and t1osc disabled ? 0.15 1.5 a3.0 pic16f610/616 ? 0.35 1.8 a5.0 ? 150 500 na 3.0 -40c t a +25c pic16hv610/616 ? 350 ? a2.0 ? 350 ? a3.0 4?50ma5.0 note 3 d021 ? 1 tbd a 2.0 wdt current (1) ?2tbd a3.0 ?8tbd a5.0 d022 ? 3 tbd a 3.0 bor current (1) ?4tbd a5.0 d023 ? 32 tbd a 2.0 comparator current (1) , both comparators enabled ?60tbd a3.0 ? 120 tbd a5.0 d024 ? 30 30 a2.0cv ref current (1) (high range) ?45 55 a3.0 ?75 95 a5.0 d025* ? 39 47 a2.0cv ref current (1) (low range) ?59 72 a3.0 ?98124 a5.0 d026 ? 45 7.0 a 2.0 t1osc current (1) , 32.768 khz ?5.08.0 a3.0 ?6.0 12 a5.0 d027 ? 0.30 1.6 a 3.0 a/d current (1) , no conversion in progress ? 0.36 1.9 a5.0 legend: tbd = to be determined * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: shunt regulator is always enabled and always draws operating current.
? 2007 microchip technology inc. preliminary ds41288c-page 145 pic16f610/616/16hv610/616 15.4 dc characteristics: pic16f610/616/16hv610/616 -e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c for extended param no. device characteristics min typ? max units conditions v dd note d020e power-down base current (i pd ) (2) ?0.05 9 a 2.0 wdt, bor, comparators, v ref and t1osc disabled ?0.15 11 a3.0 pic16f610/616 ? 0.35 15 a5.0 pic16hv610/616 ?350 ? a2.0 note 3 ?350 ? a3.0 4?200na5.0 d021e ? 1 tbd a 2.0 wdt current (1) ?2tbd a3.0 ?8tbd a5.0 d022e ? 3 tbd a 3.0 bor current (1) ?4tbd a5.0 d023e ? 32 tbd a 2.0 comparator current (1) , both comparators enabled ?60tbd a3.0 ?120tbd a5.0 d024e ? 30 70 a2.0cv ref current (1) (high range) ?45 90 a3.0 ?75120 a5.0 d025e* ? 39 91 a2.0cv ref current (1) (low range) ?59117 a3.0 ?98156 a5.0 d026e ? 4.5 25 a 2.0 t1osc current (1) , 32.768 khz ?5 30 a3.0 ?6 40 a5.0 d027e ? 0.30 12 a 3.0 a/d current (1) , no conversion in progress ?0.36 16 a5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: shunt regulator is always enabled and always draws operating current.
pic16f610/616/16hv610/616 ds41288c-page 146 preliminary ? 2007 microchip technology inc. 15.5 dc characteristics: pic16f610/616/16hv610/616-i (industrial) pic16f610/616/16hv610/616-e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions v il input low voltage i/o port: d030 with ttl buffer vss ? 0.8 v 4.5v v dd 5.5v d030a vss ? 0.15 v dd v2.0v v dd 4.5v d031 with schmitt trigger buffer vss ? 0.2 v dd v2.0v v dd 5.5v d032 mclr , osc1 (rc mode) (1) v ss ?0.2 v dd v d033 osc1 (xt and lp modes) v ss ?0.3v d033a osc1 (hs mode) v ss ?0.3 v dd v v ih input high voltage i/o ports: ? d040 with ttl buffer 2.0 ? v dd v4.5v v dd 5.5v d040a 0.25 v dd + 0.8 ? v dd v2.0v v dd 4.5v d041 with schmitt trigger buffer 0.8 v dd ?v dd v2.0v v dd 5.5v d042 mclr 0.8 v dd ?v dd v d043 osc1 (xt and lp modes) 1.6 ? v dd v d043a osc1 (hs mode) 0.7 v dd ?v dd v d043b osc1 (rc mode) 0.9 v dd ?v dd v (note 1) i il input leakage current (2) d060 i/o ports ? 0.1 1 av ss v pin v dd , pin at high-impedance d061 mclr (3) ? 0.1 5 av ss v pin v dd d063 osc1 ? 0.1 5 av ss v pin v dd , xt, hs and lp oscillator configuration d070* i pur porta weak pull-up current 50 250 400 av dd = 5.0v, v pin = v ss v ol output low voltage (4) d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v (ind.) v oh output high voltage (4) d090 i/o ports v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v (ind.) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwis e stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a sc hmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode.
? 2007 microchip technology inc. preliminary ds41288c-page 147 pic16f610/616/16hv610/616 capacitive loading specs on output pins d101* cosc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101a* c io all i/o pins ? ? 50 pf program flash memory d130 e p cell endurance 10k 100k ? e/w -40c t a +85c d130a e d cell endurance 1k 10k ? e/w +85c t a +125c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v pew v dd for erase/write 4.5 ? 5.5 v d133 t pew erase/write cycle time ? 2 2.5 ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated 15.5 dc characteristics: pic16f610/616/16hv610/616-i (industrial) pic16f610/616/16hv610/616-e (extended) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwis e stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a sc hmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode.
pic16f610/616/16hv610/616 ds41288c-page 148 preliminary ? 2007 microchip technology inc. 15.6 thermal considerations standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic typ units conditions th01 ja thermal resistance junction to ambient 70 c/w 14-pin pdip package 85.0 c/w 14-pin soic package 100 c/w 14-pin tssop package 46.3 c/w 16-pin qfn 4x4mm package th02 jc thermal resistance junction to case 32.5 c/w 14-pin pdip package 31.0 c/w 14-pin soic package 31.7 c/w 14-pin tssop package 2.6 c/w 16-pin qfn 4x4mm package th03 t die die temperature 150 c th04 pd power dissipation ? w pd = p internal + p i / o th05 p internal internal power dissipation ? w p internal = i dd x v dd (note 1) th06 p i / o i/o power dissipation ? w p i / o = (i ol * v ol ) + (i oh * (v dd - v oh )) th07 p der derated power ? w p der = pd max (t die - t a )/ ja (note 2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature.
? 2007 microchip technology inc. preliminary ds41288c-page 149 pic16f610/616/16hv610/616 15.7 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 15-5: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins 15 pf for osc2 output load condition pin
pic16f610/616/16hv610/616 ds41288c-page 150 preliminary ? 2007 microchip technology inc. 15.8 ac characteristics: pic16f610/616/16hv610/616 (industrial, extended) figure 15-6: clock timing table 15-1: clock oscillator timing requirements standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions os01 f osc external clkin frequency (1) dc ? 37 khz lp oscillator mode dc ? 4 mhz xt oscillator mode dc ? 20 mhz hs oscillator mode dc ? 20 mhz ec oscillator mode oscillator frequency (1) ? 32.768 ? khz lp oscillator mode 0.1 ? 4 mhz xt oscillator mode 1 ? 20 mhz hs oscillator mode dc ? 4 mhz rc oscillator mode os02 t osc external clkin period (1) 27 ? ? s lp oscillator mode 250 ? ns xt oscillator mode 50 ? ns hs oscillator mode 50 ? ns ec oscillator mode oscillator period (1) ? 30.5 ? s lp oscillator mode 250 ? 10,000 ns xt oscillator mode 50 ? 1,000 ns hs oscillator mode 250 ? ? ns rc oscillator mode os03 t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc os04* t os h, t os l external clkin high, external clkin low 2?? s lp oscillator 100 ? ? ns xt oscillator 20 ? ? ns hs oscillator os05* t os r, t os f external clkin rise, external clkin fall 0? ns lp oscillator 0? ns xt oscillator 0? ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unst able oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min? va lues with an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle ti me limit is ?dc? (no clock) for all devices. osc1/clkin osc2/clkout q4 q1 q2 q3 q4 q1 os02 os03 os04 os04 osc2/clkout (lp,xt,hs modes) (clkout mode)
? 2007 microchip technology inc. preliminary ds41288c-page 151 pic16f610/616/16hv610/616 table 15-2: oscillator parameters standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic freq. tolerance min typ? max units conditions os06 t warm internal oscillator switch when running (3) ???2t osc slowest clock os08 int osc internal calibrated intosc frequency (2) 1% 7.92 8.0 8.08 mhz v dd = 3.5v, 25c 2% 7.84 8.0 8.16 mhz 2.5v v dd 5.5v, 0c t a +85c 5% 7.60 8.0 8.40 mhz 2.0v v dd 5.5v, -40c t a +85c (ind.), -40c t a +125c (ext.) os10* t iosc st intosc oscillator wake- up from sleep start-up time ? 5.5 12 24 sv dd = 2.0v, -40c to +85c ?3.5714 sv dd = 3.0v, -40c to +85c ?3611 sv dd = 5.0v, -40c to +85c * these parameters are char acterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specif ied values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operati on and/or higher than expected current consumption. all devices are tested to operate at ?m in? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycl e time limit is ?dc? (no clock) for all devices. 2: to ensure these oscillato r frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 f and 0.01 f values in parallel are recommended. 3: by design.
pic16f610/616/16hv610/616 ds41288c-page 152 preliminary ? 2007 microchip technology inc. figure 15-7: clkout and i/o timing f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle table 15-3: clkout and i/o timing parameters standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions os11 t os h2 ck lf osc to clkout (1) ? ? 70 ns v dd = 5.0v os12 t os h2 ck hf osc to clkout (1) ? ? 72 ns v dd = 5.0v os13 t ck l2 io vclkout to port out valid (1) ? ? 20 ns os14 t io v2 ck h port input valid before clkout (1) t osc + 200 ns ? ? ns os15 t os h2 io vf osc (q1 cycle) to port out valid ? 50 70* ns v dd = 5.0v os16 t os h2 io if osc (q2 cycle) to port input invalid (i/o in hold time) 50 ? ? ns v dd = 5.0v os17 t io v2 os h port input valid to f osc (q2 cycle) (i/o in setup time) 20 ? ? ns os18 t io r port output rise time (2) ? ? 15 40 72 32 ns v dd = 2.0v v dd = 5.0v os19 t io f port output fall time (2) ? ? 28 15 55 30 ns v dd = 2.0v v dd = 5.0v os20* t inp int pin input high or low time 25 ? ? ns os21* t rap porta interrupt-on-change new input level time t cy ??ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 2: includes osc2 in clkout mode.
? 2007 microchip technology inc. preliminary ds41288c-page 153 pic16f610/616/16hv610/616 figure 15-8: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 15-9: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out osc start-up time internal reset (1) watchdog timer 33 32 30 31 34 i/o pins 34 note 1: asserted low. reset (1) v bor v dd (device in brown-out reset) (device not in brown-out reset) 33* 37 * 64 ms delay only if pwrte bit in the configuration word register is programmed to ? 0 ?. reset (due to bor) v bor + v hyst
pic16f610/616/16hv610/616 ds41288c-page 154 preliminary ? 2007 microchip technology inc. table 15-4: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset parameters standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions 30 t mc lmclr pulse width (low) 2 5 ? ? ? ? s s v dd = 5v, -40c to +85c v dd = 5v, +85c to +125c 31 t wdt watchdog timer time-out period (no prescaler) 7 tbd 18 18 33 tbd ms ms v dd = 5v, -40c to +85c v dd = 5v, +85c to +125c 32 t ost oscillation start-up timer period (1, 2) ? 1024 ? t osc (note 3) 33* t pwrt power-up timer period 40 65 140 ms 34* t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 s 35* v bor brown-out reset voltage tbd 2.1 tbd v (note 4) 36* v hyst brown-out reset hysteresis ? 50 ? mv 37* t bor brown-out reset minimum detection period 100 ? ? sv dd v bor legend: tbd = to be determined * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator oper- ation and/or higher than expected current consumption. all devices are tested to operate at ?min? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: by design. 3: period of the slower clock. 4: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 f and 0.01 f values in parallel are recommended.
? 2007 microchip technology inc. preliminary ds41288c-page 155 pic16f610/616/16hv610/616 figure 15-10: timer0 and timer1 external clock timings table 15-5: timer0 and timer1 external clock requirements standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ? ns 48 f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) ? 32.768 ? khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? timers in sync mode * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stat ed. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1
pic16f610/616/16hv610/616 ds41288c-page 156 preliminary ? 2007 microchip technology inc. figure 15-11: capture/compare/pwm timings (eccp) table 15-6: capture/compare/pwm requirements (eccp) standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions cc01* tccl ccp1 input low time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc02* tcch ccp1 input high time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc03* tccp ccp1 input period 3t cy + 40 n ? ? ns n = prescale value (1, 4 or 16) * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 15-5 for load conditions. (capture mode) cc01 cc02 cc03 ccp1
? 2007 microchip technology inc. preliminary ds41288c-page 157 pic16f610/616/16hv610/616 table 15-7: comparator specifications table 15-8: comparator voltage reference (cv ref ) specifications table 15-9: voltage reference specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristics min typ? max units comments cm01 v os input offset voltage ? 5.0 10 mv (v dd - 1.5)/2 cm02 v cm input common mode voltage 0 ? v dd ? 1.5 v cm03* c mrr common mode rejection ratio +55 ? ? db cm04* t rt response time falling ? 150 600 ns (note 1) rising ? 200 1000 ns cm05* t mc 2 co v comparator mode change to output valid ? ? 10 s cm06* v hys input hysteresis voltage ? 45 ? mv * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: response time is measured with one comparator input at (v dd - 1.5)/2 - 100 mv to (v dd -1.5)/2+20mv. standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristics min typ? max units comments cv01 c lsb step size (2) ? ? v dd /24 v dd /32 ? ? v v low range (vrr = 1 ) high range (vrr = 0 ) cv02 c acc absolute accuracy ? ? ? ? 1/2 1/2 lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) cv03 c r unit resistor value (r) ? 2k ? cv04 c st settling time (1) ??10 s ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from ? 0000 ? to ? 1111 ?. 2: see section 8.11 ?comparator voltage reference? for more information. vr voltage reference specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments vr01 vp6 out vp6 voltage output 0.55 0.6 0.65 v vr02 v1p2 out v1p2 voltage output 1.1 1.200 1.3 v vr03 t stable settling time ? 10 ? s * these parameters are characterized but not tested.
pic16f610/616/16hv610/616 ds41288c-page 158 preliminary ? 2007 microchip technology inc. table 15-10: shunt regulator speci fications (pic16hv610/616 only) table 15-11: PIC16F616/16hv616 a/d converter (adc) characteristics : shunt regulator characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments sr01 v shunt shunt voltage 4.75 5 5.25 v sr02 i shunt shunt current 4 ? 50 ma sr03* t settle settling time ? ? 150 ns to 1% of final value sr04 c load load capacitance 0.01 ? 10 f bypass capacitor on v dd pin sr05 i snt regulator operating current ? ? 180 a includes band gap reference current * these parameters are characterized but not tested. standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions ad01 n r resolution ? ? 10 bits bit ad02 e il integral error ? ? 1lsbv ref = 5.12v ad03 e dl differential error ? ? 1 lsb no missing codes to 10 bits v ref = 5.12v ad04 e off offset error ? 1.5 ? lsb v ref = 5.12v ad07 e gn gain error ? ? 1lsbv ref = 5.12v ad06 ad06a v ref reference voltage (3) 2.2 2.5 ?? v dd v absolute minimum to ensure 1 lsb accuracy ad07 v ain full-scale range v ss ?v ref v ad08 z ain recommended impedance of analog voltage source ?? 10k ad09* i ref v ref input current (3) 10 ? 1000 aduring v ain acquisition. based on differential of v hold to v ain . ?? 50 a during a/d conversion cycle. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: adc v ref is from external v ref or v dd pin, whichever is selected as reference input. 4: when adc is off, it will not consume any current other than leakage current. the power-down current specification includes any such leakage from the adc module.
? 2007 microchip technology inc. preliminary ds41288c-page 159 pic16f610/616/16hv610/616 table 15-12: PIC16F616/16hv616 a/d conversion requirements standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions ad130* t ad a/d clock period 1.6 ? 9.0 st osc -based, v ref 3.0v 3.0 ? 9.0 st osc -based, v ref full range a/d internal rc oscillator period 3.0 6.0 9.0 s adcs<1:0> = 11 (adrc mode) at v dd = 2.5v 1.6 4.0 6.0 sat v dd = 5.0v ad131 t cnv conversion time (not including acquisition time) (1) ?11?t ad set go/done bit to new data in a/d result register ad132* t acq acquisition time 11.5 ? s ad133* t amp amplifier settling time ? ? 5 s ad134 t go q4 to a/d clock start ? ? t osc /2 t osc /2 + t cy ? ? ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adresh and adresl registers may be read on the following t cy cycle. 2: see section 9.3 ?a/d acquisition requirements? for minimum conditions.
pic16f610/616/16hv610/616 ds41288c-page 160 preliminary ? 2007 microchip technology inc. figure 15-12: PIC16F616/16hv616 a/d conversion timing (normal mode) figure 15-13: PIC16F616/16hv616 a/d conversion timing (sleep mode) ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 6 ad134 (t osc /2 (1) ) 1 t cy ad132 ad132 ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. ad134 6 8 1 t cy (t osc /2 + t cy (1) ) 1 t cy
? 2007 microchip technology inc. preliminary ds41288c-page 161 pic16f610/616/16hv610/616 16.0 dc and ac characteristics graphs and tables graphs are not available at this time.
pic16f610/616/16hv610/616 ds41288c-page 162 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 163 pic16f610/616/16hv610/616 17.0 packaging information 17.1 package marking information * standard pic ? device marking consists of microchip part number, year code, week code, and traceability code. for pic ? device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. 14-lead pdip xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn example PIC16F616 0610017 14-lead soic (.150?) xxxxxxxxxxx xxxxxxxxxxx yywwnnn example PIC16F616-e 0610017 14-lead tssop xxxxxxxx yyww nnn example xxxx/st 0610 017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxxxxxx 16-lead qfn xxxxxxx yywwnnn 16f616 example -i/ml 0610017 -i/p 3 e
pic16f610/616/16hv610/616 ds41288c-page 164 preliminary ? 2007 microchip technology inc. 17.2 package details the following sections give the technical details of the packages. 8-lead plastic dual in-line (p or pa) ? 300 mil body [pdip] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a ? ? .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 ? ? shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb ? ? .430 n e1 note 1 d 12 3 a a1 a2 l b1 b e e e b c microchip technology drawing c04-018 b
? 2007 microchip technology inc. preliminary ds41288c-page 165 pic16f610/616/16hv610/616 14-lead plastic small outline (sl or od) ? narrow, 3.90 mm body [soic] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . significant characteristic. 3 . dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 14 pitch e 1.27 bsc overall height a ? ? 1.75 molded package thickness a2 1.25 ? ? standoff a1 0.10 ? 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 8.65 bsc chamfer (optional) h 0.25 ? 0.50 foot length l 0.40 ? 1.27 footprint l1 1.04 ref foot angle 0 ? 8 lead thickness c 0.17 ? 0.25 lead width b 0.31 ? 0.51 mold draft angle top 5 ? 15 mold draft angle bottom 5 ? 15 note 1 n d e e1 1 2 3 b e a a1 a2 l l1 c h h microchip technology drawing c04-065 b
pic16f610/616/16hv610/616 ds41288c-page 166 preliminary ? 2007 microchip technology inc. 14-lead plastic thin shrink small outline (st) ? 4.4 mm body [tssop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 14 pitch e 0.65 bsc overall height a ? ? 1.20 molded package thickness a2 0.80 1.00 1.05 standoff a1 0.05 ? 0.15 overall width e 6.40 bsc molded package width e1 4.30 4.40 4.50 molded package length d 4.90 5.00 5.10 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 ? 8 lead thickness c 0.09 ? 0.20 lead width b 0.19 ? 0.30 note 1 d n e e1 1 2 e b c a a1 a2 l1 l microchip technology drawing c04-087 b
? 2007 microchip technology inc. preliminary ds41288c-page 167 pic16f610/616/16hv610/616 16-lead plastic quad flat, no lead package (ml) ? 4x4x0.9 mm body [qfn] n otes: 1 . pin 1 visual index feature may vary, but must be located within the hatched area. 2 . package is saw singulated. 3 . dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 16 pitch e 0.65 bsc overall height a 0.80 0.90 1.00 standoff a1 0.00 0.02 0.05 contact thickness a3 0.20 ref overall width e 4.00 bsc exposed pad width e2 2.50 2.65 2.80 overall length d 4.00 bsc exposed pad length d2 2.50 2.65 2.80 contact width b 0.25 0.30 0.35 contact length l 0.30 0.40 0.50 contact-to-exposed pad k 0.20 ? ? d e n 2 1 exposed pad d2 e2 2 1 e b k n note 1 a 3 a1 a l top view bottom view microchip technology drawing c04-127 b
pic16f610/616/16hv610/616 ds41288c-page 168 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 169 pic16f610/616/16hv610/616 appendix a: data sheet revision history revision a this is a new data sheet. revision b (12/06) added pic16f610/16hv610 parts. replaced package drawings. revision c (03/2007) replaced package drawings (rev. am); replaced development support section; revised product id system. appendix b: migrating from other pic ? devices this discusses some of the issues in migrating from other pic ? devices to the pic16f6xx family of devices. b.1 pic16f676 to pic16f610/616/16hv610/616 table b-1: feature comparison feature pic16f676 pic16f610/16hv610 PIC16F616/16hv616 max operating speed 20 mhz 20 mhz 20 mhz max program memory (words) 1024 1024 2048 sram (bytes) 64 64 128 a/d resolution 10-bit none 10-bit timers (8/16-bit) 1/1 1/1 2/1 oscillator modes 8 8 8 brown-out reset y y y internal pull-ups ra0/1/2/4/5 ra0/1/2/4/5, mclr ra0/1/2/4/5, mclr interrupt-on-change ra0/1/2/3/4/5 ra0/1/2/3/4/5 ra0/1/2/3/4/5 comparator 1 2 2 eccp n n y intosc frequencies 4 mhz 8 mhz 8 mhz internal shunt regulator n y (pic16hv610) y (pic16hv616) note: this device has been designed to perform to the parameters of its data sheet. it has been tested to an electrical specification designed to determine its conformance with these parameters. due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. these differences may cause this device to perform differently in your application than the earlier version of this device.
pic16f610/616/16hv610/616 ds41288c-page 170 preliminary ? 2007 microchip technology inc. notes:
? 2007 microchip technology inc. preliminary ds41288c-page 171 pic16f610/616/16hv610/616 index a a/d specifications.................................................... 158, 159 absolute maximum ratings .............................................. 139 ac characteristics industrial and extended ............................................ 150 load conditions ........................................................ 149 adc .................................................................................... 71 acquisition requirements ........................................... 79 associated registers.................................................... 81 block diagram............................................................. 71 calculating acquisition time....................................... 79 channel selection....................................................... 72 configuration............................................................... 72 configuring interrupt ................................................... 74 conversion clock........................................................ 72 conversion procedure ................................................ 74 internal sampling switch (r ss ) impedance................ 79 interrupts..................................................................... 73 operation .................................................................... 74 operation during sleep .............................................. 74 port configuration ....................................................... 72 reference voltage (v ref )........................................... 72 result formatting........................................................ 73 source impedance...................................................... 79 special event trigger.................................................. 74 starting an a/d conversion ........................................ 73 adcon0 register............................................................... 76 adcon1 register............................................................... 77 adresh register (adfm = 0) ........................................... 78 adresh register (adfm = 1) ........................................... 78 adresl register (adfm = 0)............................................ 78 adresl register (adfm = 1)............................................ 78 analog-to-digital converter. see adc ansel register.................................................................. 32 assembler mpasm assembler................................................... 136 b block diagrams (ccp) capture mode operation ................................. 84 adc ............................................................................ 71 adc transfer function ............................................... 80 analog input model ............................................... 62, 80 ccp pwm................................................................... 88 clock source............................................................... 25 comparator c1 ........................................................... 56 comparator c2 ........................................................... 56 compare ..................................................................... 86 crystal operation ........................................................ 27 external rc mode....................................................... 28 in-circuit serial programming connections.............. 123 interrupt logic ........................................................... 116 mclr circuit............................................................. 109 on-chip reset circuit ............................................... 108 pic16f610/16hv610.................................................... 7 PIC16F616/16hv616.................................................... 8 pwm (enhanced)........................................................ 91 ra0 and ra1 pins ...................................................... 34 ra2 pins ..................................................................... 35 ra3 pin....................................................................... 36 ra4 pin....................................................................... 37 ra5 pin....................................................................... 38 rc0 and rc1 pins...................................................... 41 rc2 and rc3 pins ..................................................... 41 rc4 pin ...................................................................... 42 rc5 pin ...................................................................... 42 resonator operation .................................................. 27 timer1 ........................................................................ 47 timer2 ........................................................................ 53 tmr0/wdt prescaler ................................................ 43 watchdog timer ....................................................... 119 brown-out reset (bor).................................................... 110 associated registers................................................ 111 specifications ........................................................... 154 timing and characteristics ....................................... 153 c c compilers mplab c18.............................................................. 136 mplab c30.............................................................. 136 calibration bits.................................................................. 108 capture module. see enhanced capture/ compare/pwm (eccp) capture/compare/pwm (ccp) associated registers w/ capture/compare/ pwm..................................................... 85, 87, 103 capture mode............................................................. 84 ccp1 pin configuration ............................................. 84 compare mode........................................................... 86 ccp1 pin configuration ..................................... 86 software interrupt mode ............................... 84, 86 special event trigger ......................................... 86 timer1 mode selection................................. 84, 86 prescaler .................................................................... 84 pwm mode................................................................. 88 duty cycle .......................................................... 89 effects of reset .................................................. 90 example pwm frequencies and resolutions, 20 mhz .................................. 89 example pwm frequencies and resolutions, 8 mhz .................................... 89 operation in sleep mode.................................... 90 setup for operation ............................................ 90 system clock frequency changes .................... 90 pwm period ............................................................... 89 setup for pwm operation .......................................... 90 ccp1con (enhanced) register ........................................ 83 clock sources external modes........................................................... 26 ec ...................................................................... 26 hs ...................................................................... 27 lp ....................................................................... 27 ost .................................................................... 26 rc ...................................................................... 28 xt ....................................................................... 27 internal modes............................................................ 28 intosc .............................................................. 28 intoscio .......................................................... 28 cm1con0 register............................................................ 60 cm2con0 register............................................................ 61 cm2con1 register............................................................ 63 code examples a/d conversion .......................................................... 75 assigning prescaler to timer0.................................... 44 assigning prescaler to wdt....................................... 44 changing between capture prescalers ..................... 84 indirect addressing..................................................... 22
pic16f610/616/16hv610/616 ds41288c-page 172 preliminary ? 2007 microchip technology inc. initializing porta....................................................... 31 initializing portc....................................................... 40 saving status and w registers in ram ................... 118 code protection ................................................................ 122 comparator c2out as t1 gate ..................................................... 63 operation .................................................................... 55 operation during sleep .............................................. 59 response time ........................................................... 57 synchronizing cout w/timer1 .................................. 63 comparator analog input connection considerations........ 62 comparator hysteresis ....................................................... 64 comparator module ............................................................ 55 associated registers.................................................... 65 c1 output state versus input conditions ................... 57 comparator voltage reference (cv ref ) response time ........................................................... 57 comparator voltage reference (cv ref ) ............................ 68 effects of a reset........................................................ 59 specifications............................................................ 157 comparators c2out as t1 gate ..................................................... 48 effects of a reset........................................................ 59 specifications............................................................ 157 compare module. see enhanced capture/ compare/pwm (eccp) config register.............................................................. 107 configuration bits.............................................................. 106 cpu features ................................................................... 106 customer change notification service ............................. 175 customer notification service........................................... 175 customer support ............................................................. 175 d data memory....................................................................... 12 dc characteristics extended and industrial ............................................ 146 industrial and extended ............................................ 142 development support ....................................................... 135 device overview ................................................................... 7 e eccp. see enhanced capture/compare/pwm eccpas register ............................................................. 100 effects of reset pwm mode ................................................................. 90 electrical specifications .................................................... 139 enhanced capture/compare/pwm..................................... 83 enhanced capture/compare/pwm (eccp) enhanced pwm mode ................................................ 91 auto-restart...................................................... 101 auto-shutdown .................................................. 100 direction change in full-bridge output mode .... 97 full-bridge application ........................................ 95 full-bridge mode................................................. 95 half-bridge application ....................................... 94 half-bridge application examples..................... 102 half-bridge mode ................................................ 94 output relationships (active-high and active-low) ................................................. 92 output relationships diagram ............................ 93 programmable dead band delay ..................... 102 shoot-through current ...................................... 102 start-up considerations ...................................... 99 specifications............................................................ 156 timer resources......................................................... 83 errata .................................................................................... 6 f firmware instructions ....................................................... 125 fuses. see configuration bits g general purpose register file ........................................... 12 i id locations...................................................................... 122 in-circuit debugger........................................................... 123 in-circuit serial programming (icsp)............................... 123 indirect addressing, indf and fsr registers..................... 22 instruction format............................................................. 125 instruction set................................................................... 125 addlw..................................................................... 127 addwf..................................................................... 127 andlw..................................................................... 127 andwf..................................................................... 127 bcf .......................................................................... 127 bsf........................................................................... 127 btfsc ...................................................................... 127 btfss ...................................................................... 128 call......................................................................... 128 clrf ........................................................................ 128 clrw ....................................................................... 128 clrwdt .................................................................. 128 comf ....................................................................... 128 decf ........................................................................ 128 decfsz ................................................................... 129 goto ....................................................................... 129 incf ......................................................................... 129 incfsz..................................................................... 129 iorlw ...................................................................... 129 iorwf...................................................................... 129 movf ....................................................................... 130 movlw .................................................................... 130 movwf .................................................................... 130 nop .......................................................................... 130 retfie ..................................................................... 131 retlw ..................................................................... 131 return................................................................... 131 rlf ........................................................................... 132 rrf .......................................................................... 132 sleep ...................................................................... 132 sublw ..................................................................... 132 subwf..................................................................... 133 swapf ..................................................................... 133 xorlw .................................................................... 133 xorwf .................................................................... 133 summary table ........................................................ 126 intcon register................................................................ 18 internal oscillator block intosc specifications ........................................... 151, 152 internal sampling switch (r ss ) impedance........................ 79 internet address ............................................................... 175 interrupts........................................................................... 115 adc ............................................................................ 74 associated registers ................................................ 117 context saving ......................................................... 118 interrupt-on-change ................................................... 32 porta interrupt-on-change .................................... 116 ra2/int .................................................................... 115 timer0 ...................................................................... 116
? 2007 microchip technology inc. preliminary ds41288c-page 173 pic16f610/616/16hv610/616 tmr1 .......................................................................... 49 intosc specifications ............................................. 151, 152 ioca register..................................................................... 33 l load conditions ................................................................ 149 m mclr ................................................................................ 109 internal ...................................................................... 109 memory organization.......................................................... 11 data ............................................................................ 12 program ...................................................................... 11 microchip internet web site .............................................. 175 migrating from other pic devices ..................................... 169 mplab asm30 assembler, linker, librarian ................... 136 mplab icd 2 in-circuit debugger ................................... 137 mplab ice 2000 high-performance universal in-circuit emulator .................................................... 137 mplab integrated development environment software .. 135 mplab pm3 device programmer .................................... 137 mplab real ice in-circuit emulator system................. 137 mplink object linker/mplib object librarian ................ 136 o opcode field descriptions ............................................. 125 operational amplifier (opa) module ac specifications...................................................... 158 option register.......................................................... 17, 45 oscillator associated registers.............................................. 29, 51 oscillator module ................................................................ 25 ec ............................................................................... 25 hs ............................................................................... 25 intosc ...................................................................... 25 intoscio................................................................... 25 lp................................................................................ 25 rc............................................................................... 25 rcio ........................................................................... 25 xt ............................................................................... 25 oscillator parameters ....................................................... 151 oscillator specifications.................................................... 150 oscillator start-up timer (ost) specifications............................................................ 154 osctune register ............................................................ 29 p p1a/p1b/p1c/p1d. see enhanced capture/ compare/pwm (eccp) .............................................. 91 packaging ......................................................................... 163 marking ..................................................................... 163 pdip details.............................................................. 164 pcl and pclath ............................................................... 22 stack ........................................................................... 22 pcon register ........................................................... 21, 111 picstart plus development programmer ..................... 138 pie1 register...................................................................... 19 pin diagram pdip, soic, tssop................................................. 2, 3 qfn .......................................................................... 4, 5 pinout descriptions pic16f610/16hv610.................................................... 9 PIC16F616/16hv616.................................................. 10 pir1 register...................................................................... 20 porta................................................................................ 31 additional pin functions ............................................. 32 ansel register ................................................. 32 interrupt-on-change ........................................... 32 weak pull-ups.................................................... 32 associated registers ................................................... 39 pin descriptions and diagrams .................................. 34 ra0............................................................................. 34 ra1............................................................................. 34 ra2............................................................................. 35 ra3............................................................................. 36 ra4............................................................................. 37 ra5............................................................................. 38 specifications ........................................................... 152 porta register ................................................................. 31 portc ............................................................................... 40 associated registers ................................................... 42 p1a/p1b/p1c/p1d. see enhanced capture/ compare/pwm (eccp)...................................... 40 specifications ........................................................... 152 portc register................................................................. 40 power-down mode (sleep)............................................... 121 power-on reset (por)..................................................... 109 power-up timer (pwrt) .................................................. 109 specifications ........................................................... 154 precision internal oscillator parameters .......................... 152 prescaler shared wdt/timer0................................................... 44 switching prescaler assignment ................................ 44 program memory ................................................................ 11 map and stack (pic16f610/16hv610) ...................... 11 map and stack (PIC16F616/16hv616) ...................... 11 programming, device instructions.................................... 125 pwm mode. see enhanced capture/compare/pwm ........ 91 pwm1con register......................................................... 103 r reader response............................................................. 176 read-modify-write operations ......................................... 125 registers adcon0 (adc control 0) .......................................... 76 adcon1 (adc control 1) .......................................... 77 adresh (adc result high) with adfm = 0) ............ 78 adresh (adc result high) with adfm = 1) ............ 78 adresl (adc result low) with adfm = 0).............. 78 adresl (adc result low) with adfm = 1).............. 78 ansel (analog select) .............................................. 32 ccp1con (enhanced ccp1 control) ....................... 83 cm1con0 (c1 control) ............................................. 60 cm2con0 (c2 control) ............................................. 61 cm2con1 (c2 control) ............................................. 63 config (configuration word) ................................. 107 data memory map (pic16f610/16hv610) ................ 13 data memory map (PIC16F616/16hv616) ................ 13 eccpas (enhanced ccp auto-shutdown control) . 100 intcon (interrupt control) ........................................ 18 ioca (interrupt-on-change porta).......................... 33 option_reg (option)..................................... 17, 45 osctune (oscillator tuning).................................... 29 pcon (power control register)................................. 21 pcon (power control) ............................................. 111 pie1 (peripheral interrupt enable 1) .......................... 19 pir1 (peripheral interrupt register 1) ........................ 20 porta ....................................................................... 31 portc ....................................................................... 40 pwm1con (enhanced pwm control) ..................... 103 reset values ............................................................ 113 reset values (special registers)............................... 114
pic16f610/616/16hv610/616 ds41288c-page 174 preliminary ? 2007 microchip technology inc. special function registers ......................................... 12 special register summary ......................................... 15 srcon0 (sr latch control 0) ................................... 67 srcon1 (sr latch control 1) ................................... 67 status ...................................................................... 16 t1con ........................................................................ 50 t2con ........................................................................ 54 trisa (tri-state porta) ........................................... 31 trisc (tri-state portc) .......................................... 40 vrcon (voltage reference control) ......................... 70 wpua (weak pull up porta)................................... 33 reset................................................................................. 108 revision history ................................................................ 169 s shoot-through current ...................................................... 102 sleep power-down mode ................................................... 121 wake-up.................................................................... 121 wake-up using interrupts.......................................... 121 software simulator (mplab sim)..................................... 136 special event trigger.......................................................... 74 special function registers ................................................. 12 srcon0 register............................................................... 67 srcon1 register............................................................... 67 status register................................................................ 16 t t1con register.................................................................. 50 t2con register.................................................................. 54 thermal considerations .................................................... 148 time-out sequence........................................................... 111 timer0 ................................................................................. 43 associated registers .................................................. 45 external clock............................................................. 44 interrupt....................................................................... 45 operation .................................................................... 43 specifications............................................................ 155 t0cki .......................................................................... 44 timer1 ................................................................................. 47 associated registers.................................................... 51 asynchronous counter mode ..................................... 48 reading and writing ........................................... 48 interrupt....................................................................... 49 modes of operation .................................................... 47 operation .................................................................... 47 operation during sleep .............................................. 49 oscillator ..................................................................... 48 prescaler..................................................................... 48 specifications............................................................ 155 timer1 gate inverting gate ..................................................... 48 selecting source........................................... 48, 63 sr latch ............................................................. 66 synchronizing cout w/timer1 .......................... 63 tmr1h register ......................................................... 47 tmr1l register.......................................................... 47 timer2 associated registers.................................................... 54 timers timer1 t1con................................................................ 50 timer2 t2con................................................................ 54 timing diagrams a/d conversion ......................................................... 160 a/d conversion (sleep mode) .................................. 160 brown-out reset (bor)............................................ 153 brown-out reset situations ...................................... 110 clkout and i/o ...................................................... 152 clock timing ............................................................. 150 comparator output ..................................................... 55 enhanced capture/compare/pwm (eccp)............. 156 full-bridge pwm output............................................. 96 half-bridge pwm output .................................... 94, 102 int pin interrupt ....................................................... 117 pwm auto-shutdown auto-restart enabled......................................... 101 firmware restart .............................................. 101 pwm direction change .............................................. 97 pwm direction change at near 100% duty cycle..... 98 pwm output (active-high) ......................................... 92 pwm output (active-low) .......................................... 93 reset, wdt, ost and power-up timer ................... 153 time-out sequence case 1 .............................................................. 112 case 2 .............................................................. 112 case 3 .............................................................. 112 timer0 and timer1 external clock ........................... 155 timer1 incrementing edge ......................................... 49 wake-up from interrupt............................................. 122 timing parameter symbology .......................................... 149 trisa ................................................................................. 31 trisa register................................................................... 31 trisc ................................................................................. 40 trisc register................................................................... 40 v voltage reference (vr) specifications ........................................................... 157 voltage reference. see comparator voltage reference (cv ref ) voltage references associated registers ................................................... 65 vp6 stabilization ........................................................ 69 v ref . s ee adc reference voltage w wake-up using interrupts ................................................. 121 watchdog timer (wdt).................................................... 119 associated registers ................................................. 120 specifications ........................................................... 154 wpua register................................................................... 33 www address ................................................................. 175 www, on-line support .................... ................................... 6
? 2007 microchip technology inc. preliminary ds41288c-page 175 pic16f610/616/16hv610/616 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic16f610/616/16hv610/616 ds41288c-page 176 preliminary ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41288c pic16f610/616/16hv610/616 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2007 microchip technology inc. preliminary ds41288c-page 177 pic16f610/616/16hv610/616 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f610/616/16hv610/616, pic16f610/616/16hv610/ 616t (1) temperature range: i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package: ml = quad flat no leads (qfn) p = plastic dip sl = 14-lead small outline (3.90 mm) st = thin shrink small outline (4.4 mm) pattern: qtp, sqtp or rom code; special requirements (blank otherwise) examples: a) pic16f610/616/16hv610/616-e/p 301 = extended temp., pdip package, 20 mhz, qtp pattern #301 b) pic16f610/616/16hv610/616-i/sl = industrial temp., soic package, 20 mhz note 1: t = in tape and reel tssop and soic packages only.
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